Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.

Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.

Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.

Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.

Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.

Abstract: An IC carrier on which an integrated circuit (IC) package is loaded when electric testing of the IC package is carried out is described. The present invention enables an IC package to be loaded on or unloaded from the IC carrier smoothly without bending any of closely arranged fine leads, and prevents the lead from being deformed by falling impact when it is dropped. According to the present invention, an IC carrier for an IC package having an array of leads comprises an array of socket means for mating with the array of leads, wherein selected one of said socket means differs in an inner dimension from the other ones in the same array. The technique is applicable to both a flat IC package (QFP or SOP) and a pin grid array IC package (PGA).

Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, and an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths. The semiconductor device further includes a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a passage restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.

Abstract: An IC carrier for electric testing of an IC package enables an IC package to be loaded on or unloaded from it smoothly without bending any of closely arranged fine leads, and prevents the leads from being deformed by falling impact when it is dropped. The IC carrier for an IC package, having an array of leads, comprises an array of sockets for mating with the array of leads, wherein selected one of the sockets differs in clearance between a width of each of the sockets and a width of each of the leads to be mated from the other ones in a cross section of an array. For instance, an array of sockets having holes to mate with leads having a single diameter of an IC package are arranged so that inner diameters of the holes in an outer part of the array is larger than those in a central part of the array. The technique is applicable to both a flat IC package (QFP or SOP) and a pin grid array IC package (PGA).

Abstract: An integrated circuit device includes a package having first and second surfaces and first and second internal connection lines. A semiconductor integrated circuit chip is mounted on the first surface of the package. A first group of external connection terminals is provided on the first surface of the package, and is electrically connected to the semiconductor integrated circuit chip through the first internal connection lines. A second group of external connection terminals is provided on the second surface of the package so as to form a matrix arrangement of terminals, and is electrically connected to the semiconductor integrated circuit chip through the second internal connection lines. The second group of external connection terminals includes specific terminals specifically passing signals to be supplied to or from the semiconductor integrated circuit chip. The signals passing through the specific terminals are signals used at the time of evaluating the semiconductor integrated circuit chip.

Abstract: A semiconductor device to be mounted on a circuit board, including a semiconductor chip, a package for mounting the semiconductor chip, a plurality of conductor pads provided on the outer surface of the package, and a plurality of conductor pins, connected to the conductor pads in a substantially vertical contact condition, for connecting to the circuit board in accordance with a contacting condition.

Abstract: A semiconductor device having a semiconductor package and a radiator. The semiconductor package houses a semiconductor chip therein. The radiator includes a pillar which has a plurality of fins thereon. One end of the pillar is bonded to the semiconductor package. A hole is formed in the other end of the pillar and extends the longitudinal direction of the pillar.

Abstract: In order to protect ICs from noise it is necessary to mount a bypass capacitor as close as possible to the IC die or chip. The package must seal the die from the environment, but there are marginal spaces at the ends of a dual in line type package (DIP type package) which are not needed for the sealing function. An opening is made in the lid of the package at such a marginal area, and a chip capacitor is mounted in the opening. An additional post is provided on the lead frame. A portion of this additional post and a portion of another lead provided by the frame are exposed through the opening in the lid. The chip capacitor is soldered to the exposed portions to mechanically and electrically connect the capacitor. The additional post is scored at the edge of the package to permit easy removal of the portion thereof that would otherwise extend outside the package.

Abstract: A semiconductor device comprising at least one heat sink joined to a plurality of IC packages mounted on a mother board. Plural individual heat sinks are joined to respectively corresponding IC packages each comprising a central shaft joined to and extending in substantially perpendicular relationship from a respective said package and plural, parallel spaced fins extending outwardly from and in perpendicular relationship to the shaft.