Patents by Inventor Tetsuya Fujita

Tetsuya Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8231168
    Abstract: In an arranging structure of a wire harness for a door, the wire harness is spanned between a door of a motor vehicle and a vehicle body at an indoor side inside of a weather strip. The wire harness is drawn out from a space between a door inner panel and a door trim at the door side and is provided with an excess length portion that follows opening and closing operations of the door. The excess length portion is drawn out from the space when the door is opened. The excess length portion is drawn along an arcuate outer periphery of a speaker disposed in the space to be contained in the space when the door is closed.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: July 31, 2012
    Assignee: Sumitomo Wiring Sytems, Ltd.
    Inventors: Morihiko Toyozumi, Isao Tsuji, Daiki Nagayasu, Tsutomu Sakata, Tetsuya Fujita, Sung-Jin Kim
  • Patent number: 8091949
    Abstract: In an arrangement structure for a door wire harness, the door wire harness is arranged in a door of a vehicle body and is spanned in a space between the door and the vehicle body inside a vehicle room beyond a weather strip. The door wire harness is drawn out of a space between a door inner panel and a door trim at a door side and is fixed on the door at a wire harness drawing-out position. A door side fixing position of the door wire harness is shifted from a vehicle body side fixing position of the door wire harness in a vertical direction. A spanning section of the door wire harness between the door side fixing position and the vehicle body side fixing position is sheathed by a grommet having a flexible bellows-like tube portion and made of rubber or resin. The spanning section of the door wire harness is bent in an S-shaped configuration in a space between opposed surfaces of the door and the vehicle body when the door is closed.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 10, 2012
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Morihiro Toyozumi, Takashi Suzuki, Tetsuya Fujita, Isao Tsuji, Tsutomu Sakata, Daiki Nagayasu
  • Patent number: 8087654
    Abstract: A post-processing device include a conveyed medium stacking portion, a medium bundle stapling member, a medium bundle stacking portion and a medium bundle stacking control unit. A plurality of recording mediums, on which images are recorded, are conveyed and stacked into the conveyed medium stacking portion. The medium bundle stapling member staples a medium bundle, which is a bundle of the plurality of recording mediums stacked on the conveyed medium stacking portion, with staples. The stapled medium bundle is conveyed and stacked into the medium bundle stacking portion. The medium bundle stacking control unit stacks a second medium bundle on a first medium bundle under the condition that a second stacking stapling position deviates from a first stacking stapling position in a width direction by a distance not less than a staple width.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: January 3, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Hiroaki Awano, Toshio Endo, Tetsuya Fujita
  • Patent number: 8020920
    Abstract: A wire harness for a door is spanned between a door inner panel of a motor vehicle and a vehicle body and is arranged near an indoor side over a weather strip. An outer protective assembly includes a flange outward fitting portion that is mounted on an outer surface of a flange projecting from a door facing surface of the vehicle body and that defines a wire harness threading space for passing the wire harness. The wire harness that passes through the wire harness threading space in the flange outward fitting portion can be arranged in a vehicle body inner panel. The outer protective assembly includes an inner cover and an outer cover. The inner and outer covers are coupled to each other to define a flat space for juxtaposing electrical wires of the wire harness. The inner and outer covers are bent in a U-shaped configuration around the flange to define the flange outward fitting portion.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: September 20, 2011
    Assignee: Sumitomo Wiring Systems Ltd.
    Inventors: Morihiko Toyozumi, Isao Tsuji, Daiki Nagayasu, Tsutomu Sakata, Tetsuya Fujita, Sung-Jin Kim
  • Publication number: 20110198110
    Abstract: In a grommet fitted around a wire harness wired in a vehicle, and mounted in a through hole of a vehicle body panel, a radially outward extending portion is provided on an outer peripheral surface at an end of a small diameter cylinder portion, in which the wire harness is tightly inserted. A large diameter cylinder portion is connected to an outer peripheral end of the radially outward extending portion. An annular vehicle body engaging recessed portion is provided in an outer peripheral surface of the large diameter cylinder portion. An annular stretchable portion is provided at a portion connecting the small diameter cylinder portion to the radially outward extending portion. The stretchable portion extends in a direction same as a direction that the large diameter cylinder portion extends and is then folded backward, to form a U-shape.
    Type: Application
    Filed: October 5, 2010
    Publication date: August 18, 2011
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventor: Tetsuya FUJITA
  • Patent number: 7969237
    Abstract: A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Yousuke Hagiwara
  • Publication number: 20110081159
    Abstract: An image forming apparatus includes an image carrier member, an intermediate transfer member, a transfer unit, a cleaning unit, and a driving controller. The image carrier member carries a toner image. The toner image carried on the image carrier member is first-transferred to the intermediate transfer member. The transfer unit second-transfers the toner image first-transferred to the intermediate transfer member onto a recording medium. The cleaning unit removes residual toner on the intermediate transfer member after the second transfer. The driving controller changes a driving time of the intermediate transfer member after completion of image formation in accordance with information about a life of the intermediate transfer member.
    Type: Application
    Filed: May 25, 2010
    Publication date: April 7, 2011
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Tetsuya FUJITA
  • Publication number: 20110041481
    Abstract: Provided is a method of controlling a NOx purification system configured to reduce NOx contained in an exhaust gas by including an oxidation catalyst device (12) and a selective reduction type NOx catalyst device (14), which are arranged in this order from the upstream side, as well as the NOx purification system (1). The method and the system estimates whether a volume (Vn) of NO2 adsorbed in the oxidation catalyst device (12) increases or decreases, and controls a flow rate (Vgb) of exhaust gas which bypasses the oxidation catalyst device (12) on the basis of the increase or decrease in the estimated volume (Vn) of adsorbed NO2.
    Type: Application
    Filed: November 27, 2008
    Publication date: February 24, 2011
    Applicant: Isuzu Motors Limited
    Inventor: Tetsuya Fujita
  • Publication number: 20100283288
    Abstract: In an arrangement structure for a door wire harness, the door wire harness is arranged in a door of a vehicle body and is spanned in a space between the door and the vehicle body inside a vehicle room beyond a weather strip. The door wire harness is drawn out of a space between a door inner panel and a door trim at a door side and is fixed on the door at a wire harness drawing-out position. A door side fixing position of the door wire harness is shifted from a vehicle body side fixing position of the door wire harness in a vertical direction. A spanning section of the door wire harness between the door side fixing position and the vehicle body side fixing position is sheathed by a grommet having a flexible bellows-like tube portion and made of rubber or resin. The spanning section of the door wire harness is bent in an S-shaped configuration in a space between opposed surfaces of the door and the vehicle body when the door is closed.
    Type: Application
    Filed: May 27, 2008
    Publication date: November 11, 2010
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Morihiro Toyozumi, Takashi Suzuki, Tetsuya Fujita, Isao TsujiI, Tsutomu Sakata, Daiki Nagayasu
  • Publication number: 20100283287
    Abstract: A wire harness for a door is spanned between a door inner panel of a motor vehicle and a vehicle body and is arranged near an indoor side over a weather strip. An outer protective assembly includes a flange outward fitting portion that is mounted on an outer surface of a flange projecting from a door facing surface of the vehicle body and that defines a wire harness threading space for passing the wire harness. The wire harness that passes through the wire harness threading space in the flange outward fitting portion can be arranged in a vehicle body inner panel. The outer protective assembly includes an inner cover and an outer cover. The inner and outer covers are coupled to each other to define a flat space for juxtaposing electrical wires of the wire harness. The inner and outer covers are bent in a U-shaped configuration around the flange to define the flange outward fitting portion.
    Type: Application
    Filed: October 30, 2007
    Publication date: November 11, 2010
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Morihiko Toyozumi, Isao Tsuji, Daiki Nagayasu, Tsutomu Sakata, Tetsuya Fujita, Sung- Jin Kim
  • Publication number: 20100264687
    Abstract: In an arranging structure of a wire harness for a door, the wire harness is spanned between a door of a motor vehicle and a vehicle body at an indoor side inside of a weather strip. The wire harness is drawn out from a space between a door inner panel and a door trim at the door side and is provided with an excess length portion that follows opening and closing operations of the door. The excess length portion is drawn out from the space when the door is opened. The excess length portion is drawn along an arcuate outer periphery of a speaker disposed in the space to be contained in the space when the door is closed.
    Type: Application
    Filed: July 2, 2007
    Publication date: October 21, 2010
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Morihiko Toyozumi, Isao Tsuji, Daiki Nagayasu, Tsutomu Sakata, Tetsuya Fujita, Sung-Jin Kim
  • Publication number: 20100259316
    Abstract: A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.
    Type: Application
    Filed: November 23, 2009
    Publication date: October 14, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Fujita, Yousuke Hagiwara
  • Patent number: 7586364
    Abstract: A power supply voltage controlling circuit has a voltage regulator circuit that supplies a current to an output terminal from at least any of a first power supply and a second power supply, and compares an output voltage at the output terminal with a first reference voltage to adjust the output voltage to approach the first reference voltage; and a controller circuit that supplies the first reference voltage to the voltage regulator circuit and controls the voltage regulator circuit by outputting, to the voltage regulator circuit, at least any of a first enable signal for enabling the first power supply to supply a current to the output terminal and a second enable signal for enabling the second power supply to supply a current to the output terminal.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: September 8, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Mototsugu Hamada
  • Publication number: 20090179373
    Abstract: A post-processing device include a conveyed medium stacking portion, a medium bundle stapling member, a medium bundle stacking portion and a medium bundle stacking control unit. A plurality of recording mediums, on which images are recorded, are conveyed and stacked into the conveyed medium stacking portion. The medium bundle stapling member staples a medium bundle, which is a bundle of the plurality of recording mediums stacked on the conveyed medium stacking portion, with staples. The stapled medium bundle is conveyed and stacked into the medium bundle stacking portion. The medium bundle stacking control unit stacks a second medium bundle on a first medium bundle under the condition that a second stacking stapling position deviates from a first stacking stapling position in a width direction by a distance not less than a staple width.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 16, 2009
    Inventors: Hiroaki Awano, Toshio Endo, Tetsuya Fujita
  • Patent number: 7551019
    Abstract: This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: June 23, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Mototsugu Hamada, Hiroyuki Hara
  • Patent number: 7487370
    Abstract: According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: February 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichiro Shiratake, Yukihito Oowaki, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Masataka Matsui
  • Patent number: 7417489
    Abstract: A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: August 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Fumitoshi Hatori, Mototsugu Hamada, Hiroyuki Hara, Shinichiro Shiratake
  • Publication number: 20070285152
    Abstract: A power supply voltage controlling circuit that controls an output voltage at an output terminal to a desired set voltage, has a voltage regulator circuit that is connected to a first power supply and a second power supply that outputs a higher voltage than said first power supply, supplies a current to said output terminal from at least any of said first power supply and said second power supply, and compares the output voltage at said output terminal with a first reference voltage to adjust said output voltage to approach said first reference voltage; and a controller circuit that supplies said first reference voltage to said voltage regulator circuit and controls said voltage regulator circuit by outputting, to said voltage regulator circuit, at least any of a first enable signal for enabling said first power supply to supply a current to said output terminal and a second enable signal for enabling said second power supply to supply a current to said output terminal.
    Type: Application
    Filed: June 5, 2007
    Publication date: December 13, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya FUJITA, Mototsugu Hamada
  • Publication number: 20070236276
    Abstract: This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
    Type: Application
    Filed: June 18, 2007
    Publication date: October 11, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya FUJITA, Mototsugu Hamada, Hiroyuki Hara
  • Patent number: 7245177
    Abstract: This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: July 17, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Motosugu Hamada, Hiroyuki Hara