Abstract: According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

Abstract: According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

Abstract: A wire harness is slidably arranged between a vehicle body and an opening/dosing member of the vehicle. A grommet is fitted onto one end of a wire harness, which is arranged in the opening/closing member and is pulled out toward the vehicle body. The grommet has a diaphragm portion that can swing, extend and contract. A tube having a predetermined length is fitted onto the wire harness. A first end of the tube is fitted onto the grommet, while a second end is fixed to the wire harness, so that the tube can be slidably received in a guiding portion provided in the opening/closing member. A surplus length portion is provided in the wire harness, which is pulled out from the tube, so that the wire harness can follow opening/closing operations of the opening/closing member. The surplus length portion is received in the surplus length absorbing space provided in the guiding portion, while the wire harness is locked onto the opening/closing member at an exit of the surplus length absorbing space.

Abstract: A photomultiplier that prevents rattling between the dynodes and the base plates, the parts being fixed securely to achieve excellent vibration resistance. The dynode of the second stage (Dy2) includes a curved surface (Dy2A) having an arcuate cross-section and a flat surface (Dy2B) formed continuously and flush with the curved surface. The curved surface (Dy2A) and flat surface (Dy2B) make up the secondary electron emitting surface. Side walls (Dy2C) erected from the curved surface (Dy2A) are formed through a pressing process on either lengthwise end of the curved surface (Dy2A). First ear portions (Dy2D) extend outward from both side walls (Dy2C). Second ear portions (Dy2E) extend outward from both lengthwise ends of the flat surface (Dy2B). The first and second ear portions (Dy2D and Dy2E) are not parallel to each other but form a fixed angle.

Abstract: To provide an exhaust gas purifying system and a control method therefor, capable of burning and removing PM collected at the downstream side of a DPF by utilizing HC and CO generated when performing the operation for recovering the NOx direct reduction type catalyst from a catalyst deterioration due to poisoning with sulfur.

Abstract: A NOx purging system using a direct reduction type NOx catalyst, wherein sulfur is purged while avoiding the occurrence of secondary sulfur poisoning, taking advantage of capability of recovery from deterioration caused by sulfur poisoning at exhaust gas temperature exhibited at normal operating zone, so that the influence of sulfur poisoning can be eliminated and NOx is efficiently purged; and a method of reactivating deteriorated catalyst therein. In particular, a NOx purging system (10) comprising exhaust gas passage (2) and, arranged therein, direct reduction type NOx catalyst (3), which NOx purging system (10) is fitted with first sulfur purge control means (222) for performing such first sulfur purge operation that when exhaust gas temperature (Tg) becomes higher than given set temperature (T1) during normal operation, not only is the oxygen concentration of exhaust gas decreased but also the exhaust temperature (Tg) is raised to not below sulfur purge temperature (Tr).

Abstract: A semiconductor integrated circuit comprises a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generating circuit applying substrate biases to individual said well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

Abstract: Voltage comparator circuit capable of precisely comparing voltages to ground and power supply potentials, without level converter or plurality of power supplies. First and second MOS transistors, with gates commonly connected and drains are connected to a first power supply potential with the same gate width and length. Third MOS transistor with opposite conductive type than first and second, with drain connected to second power supply potential connected to source of first. A fourth MOS transistor with opposite conductive type to the first and second, with a drain connected to the second power supply potential, with same gate width and length as the third. The drain and gate of the first are connected, and a comparative reference potential applies to the gate of the third. Input signal is given to gate of the fourth, and output signal is derived from the drain of the second.

Abstract: A photomultiplier that prevents rattling between the dynodes and the base plates, the parts being fixed securely to achieve excellent vibration resistance. The dynode of the second stage (Dy2) includes a curved surface (Dy2A) having an arcuate cross-section and a flat surface (Dy2B) formed continuously and flush with the curved surface. The curved surface (Dy2A) and flat surface (Dy2B) make up the secondary electron emitting surface. Side walls (Dy2C) erected from the curved surface (Dy2A) are formed through a pressing process on either lengthwise end of the curved surface (Dy2A). First ear portions (Dy2D) extend outward from both side walls (Dy2C). Second ear portions (Dy2E) extend outward from both lengthwise ends of the flat surface (Dy2B). The first and second ear portions (Dy2D and Dy2E) are not parallel to each other but form a fixed angle.

Abstract: There is provided a voltage comparator circuit capable of precisely comparing voltages, particularly voltages approximating to ground and power supply potentials, without the need of any level converter means and a plurality of power supplies.

Abstract: A back gate of a P-channel MOS transistor constituting a CMOS input protection circuit or a CMOS output protection circuit, is biased by a voltage higher than a peak voltage of overshoot of an input signal or an output signal, or a back gate of an N-channel MOS transistor constituting an input protection circuit or an output protection circuit, is biased by a voltage lower than a negative peak voltage of undershoot, thereby restricting a current inflow to a substrate from an I/O terminal that might cause a latch-up in the CMOS semiconductor integrated circuit.

Abstract: In a semiconductor device operating upon receiving two power supply potentials (VDD1, VDD2) (VDD1<VDD2), the two power supplies must be simultaneously turned on, or the power supply (VDD2) must be turned on earlier than the power supply (VDD1). A substrate bias circuit for generating a substrate bias voltage operates upon receiving the power supply potential (VDD2) but cannot generate a stable substrate bias voltage before a certain time elapses after turning on the power supply (VDD2). If the power supply (VDD1) is turned on during this period, latch-up may occur. To prevent this, before a predetermined period from the time of power-on elapses, including a period after the power supply (VDD2) is turned on until the power supply VDD1 is turned on, transistors (MN1, MN2, MP1, MP2) are operated under the control of a reset circuit (14) to connect an N-well (11) to the power supply voltage (VDD2) terminal and a P-well (12) to a ground voltage (VSS) terminal.

Abstract: A circuit for shifting the potential level of an input signal toward higher potentials is added to a conventional differential ECL circuit in order to shift levels of emitter potentials of npn bipolar transistors forming a current switch toward higher potentials. Thus, the ECL circuit is improved to ensure a continuous flow of a current and to maintain stable operations even at an instant where base potentials of the npn bipolar transistors are switched by a standard ECL-level signal even when the power source voltage is around −2 V.

Abstract: CMOS logic circuit CM is of a structure in which the threshold value of constituent transistors MP1, MN1, etc. thereof is set to value lower than ordinary value, and the threshold value of a stand-by state current control P-channel MOS transistor MP2 is set to value higher than the threshold value of the transistors MP1, MN1, etc. constituting the CMOS logic circuit CM. A level conversion circuit 10 outputs a signal in which low level indicates negative voltage and high level indicates the same potential VDD as that of the first power supply line P1 in dependency upon high level and low level of signal applied to control input terminal SIG to thereby carry out ON/OFF control of the P-channel MOS transistor MP2.

Abstract: A semiconductor integrated circuit device permitting the chip area to be as small as possible without lowering the maximum arrival voltage is provided. This semiconductor integrated circuit device includes first to n-th charge pump circuits respectively driven on the basis of clocks CLK1, CLK2 to bias semiconductor substrate or well formed at the semiconductor substrate, wherein the i-th (i=1, . . . n-1) charge pump circuit is caused to be of a structure in which the current drivability is large, but the maximum arrival voltage is low as compared to the (i+1)-th charge pump circuit.

Abstract: An image forming apparatus which forms an image by transferring a developed image formed on an image holding member onto a transfer material by a transfer unit. The image forming apparatus is further provided with an induced-charge density suppressing unit. This induced-charge density suppressing unit suppresses the density of electric charge induced in the area of the image holding member which is opposite to an image forming member as a result of stoppage of the image forming member that is opposite to the image holding member and is electrostatically charged.