Abstract: In branch prediction in a superscalar processor, a fetch block address is stored in a program counter (31) to make an access to a prediction table (32) not only when a branch instruction is predicted but also when an execution history (prediction information) of the branch instruction is registered or updated on the basis of the executed result of the branch instruction.

Abstract: An A/V signal pickup unit receives an audio digital data stream. A CPU carries out a decode process, and adds tag data indicating the attribute of audio sample data to provide the same to an audio signal converter unit. The audio signal converter unit controls the timing of the output operation of sample data according to the tag data.

Abstract: There is provided a counter device comprising a master counter for counting an input signal applied thereto and a plurality of local counters disposed in a plurality of functional blocks, respectively, each for counting the input signal applied thereto, and for holding a count value corresponding to a plurality of bits of a count value of the master counter. A bus is disposed for each of the plurality of functional blocks to refer to remaining bits of the count value of the master counter.

Abstract: A branch predicting apparatus includes a prediction information buffer for supplying prediction information related to branch prediction of a branch instruction, at a same timing as fetching of an instruction fetched before the branch instruction, and a branch predicting mechanism for reading, if necessary, information required for branch prediction from a register file storing a result of operation of an instruction pipeline in accordance with the prediction information supplied from the prediction information buffer, performing branch prediction of the branch instruction by, at the latest, completion of the fetch cycle of the branch instruction, and for outputting a branch prediction signal.

Abstract: A branch execution unit processes operand data which is supplied from an instruction decoder with branch instruction information which is read from a branch target buffer, carries out branch prediction and execution, and forms a branch probability flag which is generated in relation to a branch instruction for supplying to a branch target buffer registration/update decision mechanism. In registration of a branch instruction which is non-registered in the BTB registration/update decision mechanism, the registration or non-registration is carried out in accordance with the value of the branch probability flag. Thus, it is possible to prevent a branch instruction having a low branch probability from being registered in the branch target buffer, thereby preventing reduction of branch prediction accuracy. The branch prediction is executed with employment of only a validity bit.

Abstract: A pipelined processor includes a main memory, an instruction cache, a BTB, and a BTB registration discriminator for decoding instructions line fetched from the main memory at the time of mishit of the instruction cache and for registering branch information in the BTB when the instruction is a branch instruction. Since the branch information is already stored in the BTB even at the first execution time of the branch instruction, a branch prediction hit ratio is improved.

Abstract: In a BTB, a lower part (ten-odd bits) of a branch target address obtained when a branch target generator executes a branch instruction is entered or updated as a prediction index. A linker links a prediction index signal (S1) read from the BTB with a PC output signal (S.sub.A) indicating an upper part (several bits) of a branch instruction address to generate and output a predicted target address signal (S2) in a fetch stage. A comparator compares the branch target address signal (S.sub.C) with the predicted target address signal (S2) to output a signal (S4) indicating whether they agree or not. A branch-prediction hit checking unit checks whether the branch prediction hits or misses by a result of a comparison between an execution result signal (S5) and a predicted direction signal (S3) and a result given by the signal (S4). Thus, a branch prediction system using the BTB enables reduction in volume of a BTB entry by half.

Abstract: The invention provides polyesters of terephthalic acid units and ethylene glycol units, having excellent melt moldability. The invention also provides molded articles having excellent transparency, impact resistance, gelation characteristics, appearance, tactility, mechanical properties, heat resistance, chemical resistance, and dimensional precision.

Abstract: A copolyester consisting essentially of ethylene terephthalate units and further comprising 0.01 to 1 mole % based on the sum of the moles of total diol units and the moles of triol units of a triol unit represented by the following formula (I) and/or a triol unit represented by the following formula (II). ##STR1## wherein A is a group represented by formula --CH.sub.2 CH.sub.2 -- or formula --CH(CH.sub.3)CH.sub.2 --, B is a divalent hydrocarbon group, --CO--, --SO.sub.2 --, --0-- or a direct bond (-), and p, q, r, s, t and u are each an integer of 1 to 8. A process for producing the same and molded articles (in particular extrusion blow molded articles) therefrom. The copolyesters of the present invention are applicable to melt moldings accompanying melt extrusion, in particular extrusion blow molding, where parisons therefrom have good draw-down tendency and blow moldability.

Abstract: A ketene dimer aqueous dispersion for paper sizing comprising a ketene dimer compound, an acrylamide type polymer having cationic groups and optionally an anionic dispersant and an aqueous medium is disclosed. This dispersion has a ketene dimer content as high as about 25 -30% and good storage stability.