Patents by Inventor Tetsuya Hirose

Tetsuya Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12095243
    Abstract: There is provided a supporting member having excellent durability and an apparatus including the supporting member. The supporting member includes an elastic member and a plurality of block members formed thereon. The supporting member is deformable from a shape in which end surfaces of the block members are in contact with each other to a shape in which the end surfaces are separated from each other. The elastic member includes a fixed region whose deformation is restricted by being fixed to a bottom surface of the block member, and the supporting member includes a flexure reduction unit for reducing flexure at a position near the fixed region of the elastic member.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: September 17, 2024
    Assignee: JUNKOSHA INC.
    Inventors: Daiki Hiraoka, Hiroshi Takeuchi, Yasuhiro Misu, Tetsuya Hirose
  • Patent number: 11721966
    Abstract: There is provided a supporting member having excellent durability and an apparatus including the supporting member. The supporting member includes an elastic member and a plurality of block members formed thereon. The supporting member is deformable from a shape in which end surfaces of the block members are in contact with each other to a shape in which the end surfaces are separated from each other. The elastic member includes a fixed region whose deformation is restricted by being fixed to a bottom surface of the block member, and the supporting member includes a flexure reduction unit for reducing flexure at a position near the fixed region of the elastic member.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: August 8, 2023
    Assignee: JUNKOSHA INC.
    Inventors: Daiki Hiraoka, Hiroshi Takeuchi, Yasuhiro Misu, Tetsuya Hirose
  • Patent number: 11329470
    Abstract: There is provided a supporting member having excellent durability and an apparatus including the supporting member. The supporting member includes an elastic member and a plurality of block members formed thereon. The supporting member is deformable from a shape in which end surfaces of the block members are in contact with each other to a shape in which the end surfaces are separated from each other. The elastic member includes a fixed region whose deformation is restricted by being fixed to a bottom surface of the block member, and the supporting member includes a flexure reduction unit for reducing flexure at a position near the fixed region of the elastic member.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 10, 2022
    Assignee: JUNKOSHA INC.
    Inventors: Daiki Hiraoka, Hiroshi Takeuchi, Yasuhiro Misu, Tetsuya Hirose
  • Patent number: 10472545
    Abstract: The present invention provides a sealing sheet containing a flame retardant adhesive sheet having a flame retardant-containing adhesive layer, wherein the flame retardant-containing adhesive layer has a void content of 5-40%.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 12, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Ryuuichi Kabutoya, Shigeki Muta, Masatoshi Suzuki, Tetsuya Hirose, Shinji Inokuchi
  • Patent number: 9896606
    Abstract: A PSA sheet is provided, having an adhesive face formed of an acrylic PSA layer comprising an acrylic polymer. The PSA sheet has a peel strength of 5 N/10 mm or greater. The peel strength is measured as such that the adhesive face is directly adhered to an ethylene-propylene-diene rubber surface and after 20 minutes, peeled in the 180° direction at a tensile speed of 50 mm/min.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: February 20, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Tetsuya Hirose, Shinji Inokuchi, Kenichi Nishikawa, Takayuki Shimada
  • Patent number: 9605189
    Abstract: A pressure-sensitive adhesive composition is provided for forming an acrylic pressure-sensitive adhesive that constitutes an adhesive face. The pressure-sensitive adhesive composition comprises an amino group-containing (meth)acrylate as its monomeric component. The amino group-containing (meth)acrylate accounts for 5% by mass or more of all monomeric components of the pressure-sensitive adhesive composition.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: March 28, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Tetsuya Hirose, Shinji Inokuchi, Kenichi Nishikawa, Takayuki Shimada
  • Publication number: 20160160096
    Abstract: A pressure-sensitive adhesive composition is provided for forming an acrylic pressure-sensitive adhesive that constitutes an adhesive face. The pressure-sensitive adhesive composition comprises an amino group-containing (meth)acrylate as its monomeric component. The amino group-containing (meth)acrylate accounts for 5% by mass or more of all monomeric components of the pressure-sensitive adhesive composition.
    Type: Application
    Filed: July 9, 2014
    Publication date: June 9, 2016
    Applicant: NITTO DENKO CORPORATION
    Inventors: Tetsuya Hirose, Shinji Inokuchi, Kenichi Nishikawa, Takayuki Shimada
  • Patent number: 8896378
    Abstract: A differential amplifier circuit includes a differential operational amplifier that includes a differential pair circuit and operates based on a constant bias current supplied from a bias current source circuit, and the differential amplifier circuit includes a bias current generator circuit. A current monitor circuit detects two currents flowing through the differential pair circuit in correspondence with differential input voltages inputted to the differential pair circuit, and detects a minimum current of the two currents for a difference voltage of the differential input voltages as a monitored current. A current comparator circuit compares the monitored current with the constant bias current.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Tetsuya Hirose, Yuji Osaki, Yumiko Tsuruya, Osamu Kobayashi
  • Patent number: 8828539
    Abstract: The present invention relates to an acrylic pressure-sensitive adhesive including: a) an acrylic polymer containing, as a monomer unit, an alkyl (meth)acrylate including an alkyl group having 1 to 20 carbon atoms in an amount of 50% by weight or more; and b) a tackifier resin, in which the acrylic polymer a) contains two kinds of monomer units having a difference in solubility parameter (SP value) of 0.2 (MPa)1/2 or more, each in an amount of 15% by weight or more.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: September 9, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Tetsuya Hirose, Shinji Inokuchi, Kazuhisa Maeda, Yusuke Sugino
  • Patent number: 8803725
    Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Yuji Osaki, Tetsuya Hirose
  • Patent number: 8771602
    Abstract: A resin production apparatus of the present invention includes: a reactor vessel having a vessel main body which polymerizes an ingredient to produce a thermoplastic synthetic resin which solidifies at room temperature and storing the synthetic resin in the molten state, an output mechanism disposed at a bottom part of the vessel main body, which outputs the synthetic resin in the molten state, and a temperature adjustment mechanism which adjusts temperatures of the vessel main body and the output mechanism so as to maintain the molten state of the synthetic resin; a cooling mechanism arranged below the reactor vessel, which continuously cools and solidifies the synthetic resin output from the output mechanism; and a crushing mechanism which crushes the synthetic resin fed out from the cooling mechanism.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: July 8, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Shuzo Fujiwara, Yasuhide Suzuki, Yasuhiko Okuda, Tetsuya Hirose
  • Patent number: 8692623
    Abstract: A control circuit controls first and second clock generator subcircuits so that one subcircuit of the first and second clock generator subcircuits operates for a comparison voltage generating interval, then another subcircuit operates for a clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the comparison voltage generating interval and the clock generating interval. For the comparison voltage generating interval, each of the first and second clock generator subcircuits is controlled to generate a comparison voltage and output the same voltage to an inverted output terminal of a comparator. For the clock generating interval, each of the first and second clock generator subcircuits compares an output voltage from a current-voltage converter circuit with the comparison voltage.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Seichiro Shiga, Tetsuya Hirose, Yuji Osaki
  • Patent number: 8614570
    Abstract: A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: December 24, 2013
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Tetsuya Hirose, Yuji Osaki
  • Patent number: 8436654
    Abstract: A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current detector circuit detects the generated control current, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes series-connected first and second nMOS transistors as inserted between the current detector circuit and the ground. The first nMOS transistor operates responsive to the input signal, and the second nMOS transistor operates responsive to an inverted signal of the input signal.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: May 7, 2013
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Tetsuya Hirose, Yuji Osaki, Toshihiko Mori
  • Patent number: 8421435
    Abstract: In a circuit and method for correcting a delay variation of a subthreshold CMOS circuit operating in a subthreshold region, a power supply voltage controlling circuit is provided for supplying a controlled output voltage to a subthreshold digital CMOS circuit as a controlled power supply voltage. The subthreshold digital CMOS circuit includes CMOS circuits each having a pMOSFET and an nMOSFET and operating in a subthreshold region with a predetermined delay time, and further includes a minute current generator circuit generating a predetermined minute current based on a power supply voltage, and a controlled output voltage generator circuit generating a controlled output voltage for correcting a variation in the delay time based on a generated minute current and supplying the controlled output voltage to the subthreshold digital CMOS circuit as a controlled power supply voltage including a change in each threshold voltage of the pMOSFET and the nMOSFET.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: April 16, 2013
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Tetsuya Hirose, Yuji Osaki, Kei Matsumoto
  • Publication number: 20130049875
    Abstract: A control circuit controls first and second clock generator subcircuits so that one subcircuit of the first and second clock generator subcircuits operates for a comparison voltage generating interval, then another subcircuit operates for a clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the comparison voltage generating interval and the clock generating interval. For the comparison voltage generating interval, each of the first and second clock generator subcircuits is controlled to generate a comparison voltage and output the same voltage to an inverted output terminal of a comparator. For the clock generating interval, each of the first and second clock generator subcircuits compares an output voltage from a current-voltage converter circuit with the comparison voltage.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 28, 2013
    Inventors: Seichiro SHIGA, Tetsuya Hirose, Yuji Osaki
  • Publication number: 20130009365
    Abstract: The present invention relates to a gasket mainly containing a non-halogen flame-retardant-containing adhesive sheet, wherein at least one surface of the gasket is an adhesive face of the non-halogen flame-retardant-containing adhesive sheet, and the non-halogen flame-retardant-containing adhesive sheet is an adhesive sheet wherein a non-halogen flame-retardant-containing adhesive layer/a nonporous core film/a non-halogen flame-retardant-containing adhesive layer are laminated in this order.
    Type: Application
    Filed: June 26, 2012
    Publication date: January 10, 2013
    Inventors: Ryuuichi Kabutoya, Tetsuya Hirose
  • Patent number: 8350553
    Abstract: An object of the present invention is to generate a reference voltage that is stable in relation to manufacturing process variations, by matching the operating regions of the MOSFETs contributing to generation of the reference voltage.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: January 8, 2013
    Assignee: National University Corporation Hokkaido University
    Inventors: Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya, Kenichi Ueno
  • Patent number: 8330499
    Abstract: In a comparator circuit having a differential amplifier, which makes a logical judgment by comparing an input voltage with a reference voltage, generates and outputs a resulting output voltage thereof, a current source generates and supplies a bias current of a predetermined minute current to the differential amplifier, and a first inverter circuit inverts a differential voltage from the differential amplifier. An adaptive bias current generator circuit detects the bias current of the current source, and a through current of the first inverter circuit. The adaptive bias current generator circuit generates and supplies an adaptive bias current for executing adaptive bias current control to the differential amplifier to allow the differential amplifier to operate with the bias current upon no logical judgment, and to allow the differential amplifier to operate by using the adaptive bias current obtained by increasing the bias current upon logical judgment.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Tetsuya Hirose, Keishi Tsubaki, Masahiro Numa
  • Patent number: 8305134
    Abstract: A reference current source circuit outputs a constant reference current even if surrounding environments such as temperature and power source voltage change in a power source circuit that operates in a minute current region in an order of nanoamperes. The reference current source circuit includes an nMOS-configured power source circuit, a pMOS-configured power source circuit, and a current subtracter circuit. The nMOS-configured power source circuit includes a current generating nMOSFET, and generates a first current having temperature characteristics of an output current dependent on an electron mobility. The pMOS-configured power source circuit includes a current generating pMOSFET, and generates a second current having temperature characteristics of an output current dependent on a hole mobility. The current subtracter circuit generates a constant reference current by subtracting the second current from the first current.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Tetsuya Hirose, Toyoaki Kito, Yuji Osaki