Patents by Inventor Tetsuya Hirose
Tetsuya Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110223379Abstract: A pressure-sensitive adhesive tape includes a pressure-sensitive adhesive layer as a pressure-sensitive adhesive containing a pressure-sensitive adhesive composition, a bubble, and a hollow inorganic fine particle. The hollow inorganic fine particle contains at least sodium and silicon, and the mass ratio of the sodium and the silicon that are contained in the hollow inorganic fine particle (Na/Si) is 0.5 or less. Thereby, the size of the pinhole and the number of the pinholes in the pressure-sensitive adhesive tape can be suppressed, the pinhole having a structure in which, when light is radiated onto one surface of the pressure-sensitive adhesive layer that is in the state of not being laminated on a substrate, the transmission amount of the light on the other surface thereof exceeds a predetermined threshold value, as a result of the presence of a bubble having a predetermined size or more in the pressure-sensitive adhesive layer.Type: ApplicationFiled: March 10, 2011Publication date: September 15, 2011Applicant: NITTO DENKO CORPORATIONInventors: Takuma OGAWA, Hiroyuki TSUBAKI, Shinji INOKUCHI, Tokuhisa KOSAKA, Tetsuya HIROSE
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Publication number: 20110210762Abstract: In a comparator circuit having a differential amplifier, which makes a logical judgment by comparing an input voltage with a reference voltage, generates and outputs a resulting output voltage thereof, a current source generates and supplies a bias current of a predetermined minute current to the differential amplifier, and a first inverter circuit inverts a differential voltage from the differential amplifier. An adaptive bias current generator circuit detects the bias current of the current source, and a through current of the first inverter circuit. The adaptive bias current generator circuit generates and supplies an adaptive bias current for executing adaptive bias current control to the differential amplifier to allow the differential amplifier to operate with the bias current upon no logical judgment, and to allow the differential amplifier to operate by using the adaptive bias current obtained by increasing the bias current upon logical judgment.Type: ApplicationFiled: February 28, 2011Publication date: September 1, 2011Inventors: Tetsuya HIROSE, Keishi TSUBAKI, Masahiro NUMA
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Publication number: 20110152564Abstract: A resin production apparatus of the present invention includes: a reactor vessel having a vessel main body which polymerizes an ingredient to produce a thermoplastic synthetic resin which solidifies at room temperature and storing the synthetic resin in the molten state, an output mechanism disposed at a bottom part of the vessel main body, which outputs the synthetic resin in the molten state, and a temperature adjustment mechanism which adjusts temperatures of the vessel main body and the output mechanism so as to maintain the molten state of the synthetic resin; a cooling mechanism arranged below the reactor vessel, which continuously cools and solidifies the synthetic resin output from the output mechanism; and a crushing mechanism which crushes the synthetic resin fed out from the cooling mechanism.Type: ApplicationFiled: November 15, 2010Publication date: June 23, 2011Applicant: NITTO DENKO CORPORATIONInventors: Shuzo FUJIWARA, Yasuhide SUZUKI, Yasuhiko OKUDA, Tetsuya HIROSE
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Publication number: 20110076489Abstract: Provided is an acrylic pressure-sensitive adhesive tape or sheet that shows high initial low-temperature adhesive strength, and is superior in suppression of the liner pop-off.Type: ApplicationFiled: May 20, 2009Publication date: March 31, 2011Applicant: Nitto Denko CorporationInventors: Akiko Nonaka, Shinji Inokuchi, Tetsuya Hirose
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Publication number: 20110076481Abstract: Provided is an acrylic pressure-sensitive adhesive tape or sheet having high initial low-temperature adhesive strength. The acrylic pressure-sensitive adhesive tape or sheet according to the present invention is characterized by having a bubble-mixed inorganic filler-containing acrylic pressure-sensitive adhesive layer containing an acrylic polymer formed from an acrylic monomer mixture containing an alkyl (meth)acrylate ester (a) having an alkyl group having a carbon number of 1 to 14 and a polar group-containing vinyl monomer (b) at a component rate [(a)/(b)] (by weight) of 95/5 to 91/9, an inorganic filler in the amount at a rate of 0.1 parts by weight or more and less than 2 parts by weight with respect to 100 parts by weight of the all monomer components forming the acrylic polymer and bubbles.Type: ApplicationFiled: May 20, 2009Publication date: March 31, 2011Applicant: NITTO DENKO CORPORATIONInventors: Tetsuya Hirose, Shinji Inokuchi, Akiko Nonaka
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Publication number: 20110070434Abstract: The present invention relates to an acrylic pressure-sensitive adhesive including: a) an acrylic polymer containing, as a monomer unit, an alkyl (meth)acrylate including an alkyl group having 1 to 20 carbon atoms in an amount of 50% by weight or more; and b) a tackifier resin, in which the acrylic polymer a) contains two kinds of monomer units having a difference in solubility parameter (SP value) of 0.2 (MPa)1/2 or more, each in an amount of 15% by weight or more.Type: ApplicationFiled: March 16, 2009Publication date: March 24, 2011Applicant: NITTO DENKO CORPORATIONInventors: Tetsuya Hirose, Shinji Inokuchi, Kazuhisa Maeda, Yusuke Sugino
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Publication number: 20110025285Abstract: In a circuit and method for correcting a delay variation of a subthreshold CMOS circuit operating in a subthreshold region, a power supply voltage controlling circuit is provided for supplying a controlled output voltage to a subthreshold digital CMOS circuit as a controlled power supply voltage. The subthreshold digital CMOS circuit includes CMOS circuits each having a pMOSFET and an nMOSFET and operating in a subthreshold region with a predetermined delay time, and further includes a minute current generator circuit generating a predetermined minute current based on a power supply voltage, and a controlled output voltage generator circuit generating a controlled output voltage for correcting a variation in the delay time based on a generated minute current and supplying the controlled output voltage to the subthreshold digital CMOS circuit as a controlled power supply voltage including a change in each threshold voltage of the pMOSFET and the nMOSFET.Type: ApplicationFiled: February 26, 2010Publication date: February 3, 2011Inventors: Tetsuya HIROSE, Yuji OSAKI, Kei MATSUMOTO
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Publication number: 20100225384Abstract: A reference current source circuit is provided which is capable of outputting a constant reference current even if surrounding environments such as temperature and power source voltage change in a power source circuit that operates in a minute current region in an order of nanoamperes. The reference current source circuit includes an nMOS-configured power source circuit, a pMOS-configured power source circuit, and a current subtracter circuit. The nMOS-configured power source circuit includes a current generating nMOSFET, and generates a first current having temperature characteristics of an output current dependent on an electron mobility. The pMOS-configured power source circuit includes a current generating pMOSFET, and generates a second current having temperature characteristics of an output current dependent on a hole mobility. The current subtracter circuit generates a constant reference current by subtracting the second current from the first current.Type: ApplicationFiled: February 26, 2010Publication date: September 9, 2010Inventors: Tetsuya HIROSE, Toyoaki KITO, Yuji OSAKI
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Publication number: 20100164461Abstract: An object of the present invention is to generate a reference voltage that is stable in relation to manufacturing process variations, by matching the operating regions of the MOSFETs contributing to generation of the reference voltage.Type: ApplicationFiled: July 16, 2008Publication date: July 1, 2010Inventors: Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya, Kenichi Ueno
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Publication number: 20100021730Abstract: Disclosed is an acrylic pressure-sensitive adhesive tape or sheet that exhibits satisfactory adhesion to hard-to-adhere adherends. The acrylic pressure-sensitive adhesive tape or sheet includes a microsphere-containing viscoelastic layer (X); and a pressure-sensitive adhesive layer (Y) arranged on at least one side of the viscoelastic layer (X). The pressure-sensitive adhesive layer (Y) is derived from an acrylic pressure-sensitive adhesive composition through the application of an active energy ray, and the acrylic pressure-sensitive adhesive composition contains (a) a vinyl monomer mixture mainly containing an alkyl(meth)acrylate (a1) whose alkyl moiety has 2 to 14 carbon atoms, or a partial polymer of the vinyl monomer mixture; (b) a photoinitiator; and (c) an alkylphenol tackifier. The acrylic pressure-sensitive adhesive composition preferably contains 0.001 to 5 parts by weight of the photoinitiator (b) and 0.Type: ApplicationFiled: October 10, 2007Publication date: January 28, 2010Applicant: NITTO DENKO CORPORATIONInventors: Takashi Kondou, Mitsuyoshi Shirai, Masanori Uesugi, Masayuki Okamoto, Kazuhisa Maeda, Tetsuya Hirose, Shinji Inokuchi
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Patent number: 7642633Abstract: An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer substrate, and the memory chip is sealed to the front surface of the interposer substrate to constitute an encapsulated capsule type semiconductor package. On the other hand, a logic chip is prepared. Further, a main substrate is prepared in which electrodes are formed on the front surface and on the rear surface, respectively, and desired internal connections are provided between these electrodes.Type: GrantFiled: February 6, 2006Date of Patent: January 5, 2010Assignee: Renesas Technology Corp.Inventors: Tetsuya Hirose, Naoyuki Shinonaga, Shuichi Osaka
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Publication number: 20090174051Abstract: A package structure which aims at improvement in function, miniaturization, and systematization of a semiconductor integrated circuit having been made into multichip is offered. A substrate in which a plurality of terminals for a test and a plurality of terminals for external connection are arranged on the front surface, and a plurality of terminals for internal connection are arranged on the back surface, and a semiconductor chip in which a plurality of surface terminals connected to an internal circuit are formed in the front surface are prepared. An encapsulated semiconductor package is formed by joining the back surface of this semiconductor chip to the back surface of the substrate, connecting the surface terminal of the semiconductor chip to the desired terminal for internal connection of the substrate, and sealing the semiconductor chip on the back surface of the substrate with a molded member.Type: ApplicationFiled: January 12, 2005Publication date: July 9, 2009Inventors: Shuichi Osaka, Hitoshi Fujimoto, Tetsuya Hirose, Naoyuki Shinonaga
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Publication number: 20060175715Abstract: An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer substrate, and the memory chip is sealed to the front surface of the interposer substrate to constitute an encapsulated capsule type semiconductor package. On the other hand, a logic chip is prepared. Further, a main substrate is prepared in which electrodes are formed on the front surface and on the rear surface, respectively, and desired internal connections are provided between these electrodes.Type: ApplicationFiled: February 6, 2006Publication date: August 10, 2006Inventors: Tetsuya Hirose, Naoyuki Shinonaga, Shuichi Osaka
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Patent number: 6660789Abstract: A polyester composition comprising (A) 30 to 95 parts by weight of a polybutylene terephthalate resin containing a polybutylene terephthalate-isophthalate copolymer in which the content of an isophthalic acid ingredient to the entire dicarboxylic acid ingredient is 5 to 20 mol %, (B) 1 to 30 parts by weight of a polycarbonate resin, (C) 3 to 20 parts by weight of an elastomer and (D) 15 to 30 parts by weight of a fibrous reinforcing material, and (E) 0.1 to 3 parts by weight of a silicone compound, wherein the total amount for (A)-(D) is 100 parts by weight, the composition being used for insert molding.Type: GrantFiled: March 21, 2002Date of Patent: December 9, 2003Assignees: Toray Industries, Inc., Denso CorporationInventors: Tomoyuki Uno, Takashi Sugata, Akira Hirai, Tetsuya Hirose, Hiroyuki Yamazaki, Kazuo Kato
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Patent number: 6530764Abstract: A resin-sealing mold for encapsulating a semiconductor device includes upper and lower molds with a first cavity insert forming a cavity side face portion; a first elastic post supporting the first cavity insert; an elastic plate, built in the first cavity insert, forming a cavity bottom portion; a second cavity insert embedded at a position adjacent to the elastic plate on the side opposite to the cavity; a second elastic post supporting the second cavity insert; a retainer including the first cavity insert and the second cavity insert; and a backing plate to which the first elastic post, the second elastic post and the retainer are attached. Generation of thin burrs that tend to appear on the periphery of the package and in the vicinity of the cull section is prevented, and, consequently, a resin-sealing mold with high reliability is produced.Type: GrantFiled: January 29, 2001Date of Patent: March 11, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshiyuki Mishima, Tetsuya Hirose, Hideji Aoki, Hiromichi Yamada, Toru Ueno, Kiyoharu Kato
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Publication number: 20020188073Abstract: A polyester type resin composition comprising (A) 30 to 95 parts by weight of a polybutylene terephthalate type resin containing a polybutylene terephthalate-isophthalate copolymer in which the content of an isophthalic acid ingredient to the entire dicarboxylic acid ingredient is 3 to 30 mol %, (B) 1 to 30 parts by weight of a polycarbonate resin, (C) 1 to 30 parts by weight of an elastomer and (D) 3 to 60 parts by weight of a fibrous reinforcing material, wherein the total amount for (A)-(D) is 100 parts by weight, the composition being used for insert molding.Type: ApplicationFiled: March 21, 2002Publication date: December 12, 2002Inventors: Tomoyuki Uno, Takashi Sugata, Akira Hirai, Tetsuya Hirose, Hiroyuki Yamazaki, Kazuo Kato
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Patent number: 6447913Abstract: To provide a thermoplastic polyester resin composition which has a very good durability to alkaline solutions for a long period of time. That is, a thermoplastic polyester resin composition, wherein a thermoplastic polyester resin (A) is compounded with 1-25% by weight (in the total composition) of impact resistance rendering materials (B), 0.1-15% by weight (in the total composition) of a silicone compound and/or a fluorine compound (C), 1-50% by weight (in the total composition) of an inorganic filler (D), and 0.1-10% by weight of at least one polyfunctional compound (E) selected from the group consisting of an epoxy compound, an isocyanate compound and a carboxylic acid dianhydride. A molded article of the present invention has anti-stress properties even in a weld part thereof.Type: GrantFiled: January 25, 2001Date of Patent: September 10, 2002Assignees: Polyplastics Co., LTD, Denso CorporationInventors: Kazufumi Watanabe, Takayuki Ishikawa, Toru Katsumata, Tetsuya Hirose, Hiroyuki Wakabayashi
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Publication number: 20020012716Abstract: In a resin-sealing mold of a semiconductor device, each of the upper and lower molds is provided with: a first cavity insert for forming a cavity side face portion; a first elastic post for supporting the first cavity insert; an elastic plate, built in the first cavity insert, for forming a cavity bottom portion; a second cavity insert embedded at a position adjacent to the elastic plate on the side opposite to the cavity; a second elastic post for supporting the second cavity insert; a retainer including the first cavity insert and the second cavity insert; and a backing plate to which the first elastic post, the second elastic post and the retainer are attached. It becomes possible to prevent the generation of thin burrs that tend to appear on the periphery of the package and in the vicinity of the cull section, and consequently to provide a resin-sealing mold with high reliability.Type: ApplicationFiled: January 29, 2001Publication date: January 31, 2002Inventors: Yoshiyuki Mishima, Tetsuya Hirose, Hideji Aoki, Hiromichi Yamada, Toru Ueno, Kiyoharu Kato
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Patent number: 5333505Abstract: In a semiconductor pressure sensor, a dam which prevents a sheathing resin from flowing into a diaphragm portion during the molding of the sheathing resin is disposed on the outer periphery of piezoresistors and the diaphragm portion on the surface of a semiconductor pressure sensor chip. The volume of the base and that of the semiconductor pressure sensor chip are adjusted so that a tensile force exerted upon the semiconductor pressure sensor chip by the base cancels a compressive force exerted upon the semiconductor pressure sensor by the sheathing resin when the temperature of the semiconductor pressure sensor returns to an ordinary room temperature from a high temperature. As a result, strain is not caused in the semiconductor pressure sensor chip, and therefore measurements of pressure with a high degree of accuracy can be performed.Type: GrantFiled: January 12, 1993Date of Patent: August 2, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshiharu Takahashi, Tetsuya Hirose, Hiroshi Otani, Seiji Takemura
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Patent number: 5207102Abstract: A semiconductor pressure sensor is manufactured by integrally encapsulating a semiconductor pressure, sensor chip, a pedestal, leads, wires and a die pad in an outer package except for the surface of a diaphragm of the semiconductor pressure sensor chip and the reverse side of the die pad. The ratio of the thickness of the pedestal to the thickness of the semiconductor pressure sensor chip is 7.5 or less, while the ratio of the diameter of an opening formed in the outer package at the surface of the diaphragm and the diameter of the diaphragm is 1 or more. The thermal stress generated in the semiconductor pressure sensor chip can freely be reduced to a desired value, and a semiconductor pressure sensor exhibiting a desired accuracy can therefore be obtained. Furthermore, since the semiconductor pressure sensor can be manufactured by an ordinary IC manufacturing process, a semiconductor pressure sensor with reduced cost and having high quality can be produced.Type: GrantFiled: September 20, 1991Date of Patent: May 4, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshiharu Takahashi, Tetsuya Hirose, Hideyuki Ichiyama