Abstract: In a three-dimensional object manufacturing method using a three-dimensional object manufacturing device for manufacturing a three-dimensional object by layering and stacking an ink layer in which a surface is flattened by a flattening roller for removing one part of the surface of the ink layer to adjust a thickness of the ink layer to a thickness t, where when forming ink layers with an inkjet head, an ink ejection amount reduction region in which an ejection amount of ink ejected by the inkjet head is reduced from an amount corresponding to the thickness t in a part corresponding to an interior of the three-dimensional object, and when forming the ink layers on an upper side of the specific ink layers with the inkjet head, an ejection amount of ink ejected by the inkjet head is increased from an amount corresponding to the thickness t.

Abstract: A building apparatus building a three-dimensional object includes: an inkjet head serving as an ejection head; and a scan driver. The scan driver causes the inkjet head to perform a main scanning operation and a sub scanning operation. In an operation of forming one layer, the scan driver causes the inkjet head to perform the main scanning operation a certain number of times Pn (Pn is an integer equal to or greater than two), for each position of the layer being built, and to form, as the one layer, a layer configured such that a plurality of blocks formed by performing the Pn main scanning operations are arranged in a row in a sub scanning direction. Each of the blocks includes an intermediate region and an end region. The manner of forming the end region in the corresponding block is differentiated between two layers continuously overlapping in the deposition direction.

Abstract: In a three-dimensional object manufacturing method using a three-dimensional object manufacturing device for manufacturing a three-dimensional object by layering and stacking an ink layer in which a surface is flattened by a flattening roller for removing one part of the surface of the ink layer to adjust a thickness of the ink layer to a thickness t, where when forming ink layers with an inkjet head, an ink ejection amount reduction region in which an ejection amount of ink ejected by the inkjet head is reduced from an amount corresponding to the thickness t in a part corresponding to an interior of the three-dimensional object, and when forming the ink layers on an upper side of the specific ink layers with the inkjet head, an ejection amount of ink ejected by the inkjet head is increased from an amount corresponding to the thickness t.

Abstract: An ink supplying system includes a weight measuring portion that measures at least a weight of the ink, and an ink refilling pump that extracts the ink from a refill container capable of refilling the ink to an ink container and refills the ink to the ink container; the controller controls the ink refilling pump to refill the ink from the refill container to the ink container when the weight of the ink measured by the weight measuring portion becomes smaller than or equal to a predetermined set value; and the set value is changeable.

Abstract: A building apparatus building a three-dimensional object includes: an inkjet head serving as an ejection head; and a scan driver. The scan driver causes the inkjet head to perform a main scanning operation and a sub scanning operation. In an operation of forming one layer, the scan driver causes the inkjet head to perform the main scanning operation a certain number of times Pn (Pn is an integer equal to or greater than two), for each position of the layer being built, and to form, as the one layer, a layer configured such that a plurality of blocks formed by performing the Pn main scanning operations are arranged in a row in a sub scanning direction. Each of the blocks includes an intermediate region and an end region. The manner of forming the end region in the corresponding block is differentiated between two layers continuously overlapping in the deposition direction.

Abstract: A semiconductor device includes a semiconductor substrate, a first lower-layer line for supplying power to a transistor formed on the semiconductor substrate, a first interlayer line which is connected to the first lower-layer line, and an allowable current of which is larger than that of the first lower-layer line; and an upper-layer line which is provided above the first interlayer line and receives power input from outside. The first interlayer line is connected to the upper-layer line through a switch circuit formed on the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device, including forming a circuit block in a peripheral edge portion of a semiconductor chip, forming a circuit block pad on the circuit block to provide an electrical interface for the circuit block, and forming a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and providing a bonding wire pad for the circuit block.

Abstract: A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and electrically connected to a lead frame by a bonding wire, the laterally offset bonding pad thereby functioning as a substitute wire bonding pad for the circuit block.

Abstract: An ESD analysis method and computer program product are disclosed. A circuit simulation is executed of design data of a semiconductor integrated circuit including a first power supply pad, a second power supply pad and a plurality of current paths between the first power supply pad and the second power supply pad, to calculate potentials in the plurality of current paths, when one of an ESD current and an ESD voltage is applied between the first power supply pad and the second power supply pad. An ESD tolerance is checked by calculating a potential difference between a first node coupled to the first power supply pad and a second node coupled to the second power supply pad, based on the calculated potentials. The first node and the second node are determined as nodes to be coupled to a border cell upon the potential difference being lower than a predetermined value.

Abstract: A semiconductor device of the present invention includes a plurality of switch cells having a switch transistor that controls conducting states of a global power supply line and a local power supply line according to a control signal, and a delay circuit that delays the control signal and transmits the control signal to the switch transistor connected to a subsequent stage, a chain unit that receives the control signal from outside, transmits the control signal by the delay circuit connected in series, and sequentially conducts the switch transistor, and a tree unit that is provided with the control signal via the switch cells disposed in a last stage of the chain unit, distributes the control signal to a plurality of groups by the delay circuit connected in parallel, and conducts the switch transistor in parallel by the distributed control signal.

Abstract: A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Abstract: A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Abstract: A semiconductor device includes a semiconductor substrate which includes a functional circuit, a trunk wiring which passes through a portion near a position immediately above a center portion of the functional circuit, a power supply pad which is connected to an end of the trunk wiring and placed at a layer level which is same as a layer level where the trunk wiring is placed, and a connection wiring which connects a substantially center portion of the functional circuit and the trunk wiring.

Abstract: A method of fabricating a semiconductor device, including forming a circuit block in a peripheral edge portion of a semiconductor chip, forming a circuit block pad on the circuit block to provide an electrical interface for the circuit block, and forming a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and providing a bonding wire pad for the circuit block.

Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.

Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.

Abstract: A semiconductor device of the present invention includes a plurality of switch cells having a switch transistor that controls conducting states of a global power supply line and a local power supply line according to a control signal, and a delay circuit that delays the control signal and transmits the control signal to the switch transistor connected to a subsequent stage, a chain unit that receives the control signal from outside, transmits the control signal by the delay circuit connected in series, and sequentially conducts the switch transistor, and a tree unit that is provided with the control signal via the switch cells disposed in a last stage of the chain unit, distributes the control signal to a plurality of groups by the delay circuit connected in parallel, and conducts the switch transistor in parallel by the distributed control signal.

Abstract: A semiconductor device includes a semiconductor substrate which includes a functional circuit, a trunk wiring which passes through a portion near a position immediately above a center portion of the functional circuit, a power supply pad which is connected to an end of the trunk wiring and placed at a layer level which is same as a layer level where the trunk wiring is placed, and a connection wiring which connects a substantially center portion of the functional circuit and the trunk wiring.

Abstract: The present invention aims to offer a urea grease composition which excels in noise performance, has long life at high temperatures and, further, also provides the basic performance of greases such as shear stability and heat resistance, as well as appropriate oil separation properties. The present invention provides a urea grease composition comprising: a diurea compound as shown by the General Formula (A) below: R11 NHCONHR12NHCONHR13 . . . (A), (where R11 and R13 are groups selected from the group consisting of hydrocarbon groups having from 6 to 20 carbons, at least one of R11 and R13 is a dodecyl group and R12 is a diphenylme thane group); and a diurea compound as shown by the General Formula (B) below: R21 NHCONHR22NHCONHR23 . . . (B), (where R21 and R23 are groups selected from the group consisting of hydrocarbon groups having from 6 to 20 carbons, at least one of R21 and R23 is an oleyl group, and R22 is a diphenylmethane group).

Abstract: A semiconductor device includes a semiconductor substrate, a first lower-layer line for supplying power to a transistor formed on the semiconductor substrate, a first interlayer line which is connected to the first lower-layer line, and an allowable current of which is larger than that of the first lower-layer line; and an upper-layer line which is provided above the first interlayer line and receives power input from outside. The first interlayer line is connected to the upper-layer line through a switch circuit formed on the semiconductor substrate.