Patents by Inventor Tetsuya Kawamura
Tetsuya Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080024691Abstract: A normal transistor CTFT connected to a data signal line DL and a pixel electrode PX and a spare transistor FTFT in a floating state are formed on a gate line GL. When an operational abnormality occurs in the normal transistor CTFT, the normal transistor CTFT is cut off from the data signal line DL and the pixel electrode PX by cutting lines CL. The spare transistor FTFT is connected to the data signal line DL and the pixel electrode PX by repair lines RL.Type: ApplicationFiled: April 4, 2007Publication date: January 31, 2008Inventors: Noriyuki Okabe, Tetsuya Kawamura, Masashi Sato, Kenta Kamoshida
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Patent number: 7161641Abstract: A liquid crystal display device comprising a pair of substrates with liquid crystal layer therebetween, a plurality of gate signal lines and a plurality of drain signal lines formed on one of the pair of substrates, at least a pixel electrode and a plurality of counter electrodes formed on the one of the pair of substrates in each pixels, at least one of the plurality of counter electrodes extend along a drain signal line overlapping to the drain signal lines with at least one of an insulation film therebetween, and the drain signal line has two or more regions which differ in distance between a surface of the drain signal line and the counter electrode.Type: GrantFiled: October 14, 2004Date of Patent: January 9, 2007Assignee: Hitachi, Ltd.Inventors: Yoshiaki Nakayoshi, Nagatoshi Kurahashi, Tetsuya Kawamura, Kazuhiko Yanagawa
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Publication number: 20060285057Abstract: To suppress occurrence of low temperature bubbles while securing pressure resistance to external forces applied to substrates of a liquid crystal display device, a plurality of spacers disposed between the substrates are divided into a plurality of spacer groups 2, one unit of which is configured with spacers 2a, 2b allocated in close proximity to each other; and the spacer groups 2 are disposed with a density that the low temperature bubbles do not occur. Hence, the strength of the substrates increases, and in a region 10 where no spacers exist, a large deformation of the substrates by shrinkage is allowed, and a liquid crystal layer 8 is sufficiently enough shrunk even under a low temperature environment to prevent the low temperature bubbles from occurring.Type: ApplicationFiled: May 17, 2006Publication date: December 21, 2006Applicant: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Tetsuya Kawamura, Katsuhiko Inada, Akimasa Toyama
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Publication number: 20060232532Abstract: A display device includes a substrate having display portion and peripheral portion, a plurality of gate signal lines and a plurality of drain signal lines formed over the substrate, a plurality of switching elements connected to the plurality of gate signal lines and the plurality of drain signal lines and formed over the substrate, and a plurality of pixel electrodes connected to the plurality of switching elements and formed in the display portion. An organic interlayer film is formed in the display portion and the peripheral portion, and a covering layer is formed on the organic interlayer film in the peripheral portion and the insulating film includes at least one of a plurality of recesses and protuberances.Type: ApplicationFiled: June 14, 2006Publication date: October 19, 2006Inventors: Tetsuya Kawamura, Kazuhiko Yanagawa, Nagatoshi Kurahashi, Tsuyoshi Uchida
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Publication number: 20060192738Abstract: A liquid crystal display device includes a first substrate, a second substrate, and a liquid crystal supported between the first substrate and the second substrate. A signal line, a pixel electrode, and a thin film transistor are formed on the first substrate and electrically connected to the signal line and the pixel electrode, and a drain driver supplies a gray scale voltage to the pixel electrode. Plural voltage-dividing resistance elements are formed on the first substrate, and supply plural gray scale reference voltages to the drain driver. The plural voltage-dividing resistance elements and the signal line are constructed of a same wiring material.Type: ApplicationFiled: April 19, 2006Publication date: August 31, 2006Inventors: Tetsuya Kawamura, Yoshihiro Imajo
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Patent number: 7095048Abstract: Dummy holes 36 are made for every one of display dot 5a, 5b and 5c at pixels 5 through interlayer film 33 up to gate electrode and scanning lines 11 before interlayer film 33 on glass substrate 3 is washed. When interlayer film 33 is washed, electric charges stored at semiconductor layer 21 are substantially the same in quantity as those stored at gate electrode and scanning lines 11 through dummy holes 36. Thus, electric potentials at gate electrode and scanning lines 11 are substantially equal in magnitude to those at semiconductor layer 21. This can suppress the occurrence of voltage differences imposed between gate electrode and scanning lines 11 and semiconductor layer 21.Type: GrantFiled: November 29, 2004Date of Patent: August 22, 2006Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventor: Tetsuya Kawamura
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Patent number: 7064351Abstract: Poly-silicon semiconductor layer 21 and dummy poly-silicon semiconductor layer 25 are formed in insulation from each other on glass substrate. Gate insulation film 31 is formed on poly-silicon semiconductor layer 21, dummy poly-silicon semiconductor layer 25 and glass substrate and covered with scanning and gate lines 11, which is overlapped with poly-silicon semiconductor layer 21 and dummy poly-silicon semiconductor layer 25. Poly-silicon semiconductor layer 21 is coupled with a reference potential to define capacitor Cc and also with scanning and gate line 11 to define capacitor Cd. Likewise, dummy poly-silicon semiconductor layer 25 is coupled with a reference potential to define capacitor Cc and also with scanning and gate line 11 to define capacitor Cd. Capacitors Cc and Cd suppress increase in voltage applied to gate insulation film 31 between scanning and gate line 11 and poly-silicon semiconductor layer 21 due to electrostatic charges.Type: GrantFiled: August 5, 2004Date of Patent: June 20, 2006Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventor: Tetsuya Kawamura
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Patent number: 7064734Abstract: A display device includes a substrate having display portion and peripheral portion, a plurality of gate signal lines and a plurality of drain signal lines formed over the substrate, a plurality of switching elements connected to the plurality of gate signal lines and the plurality of drain signal lines and formed over the substrate, and a plurality of pixel electrodes connected to the plurality of switching elements and formed in the display portion. An organic interlayer film is formed in the display portion and the peripheral portion, an insulating film is formed between the substrate and the organic interlayer film in the display portion and the peripheral portion, and the insulating film includes at least one of a plurality of recesses and protuberances.Type: GrantFiled: March 19, 2003Date of Patent: June 20, 2006Assignee: Hitachi, Ltd.Inventors: Tetsuya Kawamura, Kazuhiko Yanagawa, Nagatoshi Kurahashi, Tsuyoshi Uchida
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Patent number: 7038675Abstract: In a liquid crystal display device formed of a plurality of a liquid crystal display elements in which a liquid crystal material is supported between first and second substrates, plural semiconductor chips for operating the liquid crystal display elements, and a power source circuit, a resistance voltage-dividing circuit is mounted on a peripheral portion along one side of the first substrate, which resistance voltage-dividing circuit divides the voltage supplied from the power source circuit and supplies the divided voltage to each of the semiconductor chips. This allows the resistance voltage-dividing circuit to be easily modified, so that the period until the product forwarding of the liquid crystal display devices is shortened without increasing the cost even after various kinds of design changes have been implemented.Type: GrantFiled: September 25, 2002Date of Patent: May 2, 2006Assignee: Hitachi, Ltd.Inventors: Tetsuya Kawamura, Yoshihiro Imajo
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Publication number: 20060077333Abstract: In a liquid crystal display comprising a plurality of pixels each of which has an switching element, a plurality of drain drivers and gate drivers for operating the switching elements and the pixels, and a plurality of drain lines and gate lines supplying signals from the drain drivers and the gate drivers to the switching elements being formed on one of a pair of substrates sandwiching a liquid crystal layer, the present invention provides wiring lines formed on the one of a pair of substrates for transferring display data signals and a clock signal between each pair of the plurality of drain drivers adjacent to one another, and provides at least one gate circuit for at least one of the plurality of drain drivers which is controlled by the clock signal and switches the display data signals and the clock signal either (1) to be acquired by the at least one of the plurality of drain drivers or (2) to be transferred to another of the plurality of drain drivers arranged adjacent to the at least one of the pluralType: ApplicationFiled: November 22, 2005Publication date: April 13, 2006Inventors: Yoshihiro Imajo, Tetsuro Izawa, Kimitoshi Ohgiichi, Hiroshi Okawara, Shiro Ueda, Nobuyuki Ishige, Tetsuya Kawamura, Hisashi Ishino, Fumiaki Komori
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Publication number: 20060065645Abstract: A region surrounded by two gate wiring and two drain wiring includes pixels and when there is a defect of short-circuit in adjacent pixel electrodes, the short-circuited portion is removed by irradiating a laser via a mask having a transmission pattern, which corresponds to a pattern of the gate wiring, drain wiring and pixel electrodes in the short-circuited portion. The above short-circuited portion is identified and removed in comparison to a normal pattern, by use of information from an inspection apparatus, and the pattern defect formed on the substrate is automatically repaired. By applying the above method to a manufacturing process of display apparatus, in particular, to a resist pattern forming process, a display apparatus having a highly qualified display property may be achieved.Type: ApplicationFiled: June 3, 2005Publication date: March 30, 2006Inventors: Nobuaki Nakasu, Kaoru Yamada, Yuichiro Tanaka, Takeshi Arai, Hideyuki Honoki, Kazushi Yoshimura, Tetsuya Kawamura, Masanori Okawa
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Patent number: 6989881Abstract: A display device having a substrate, and a display area and a peripheral area being formed on the substrate. A signal line is extended from the display area to the peripheral area on the substrate, and the signal line at the peripheral area is covered with a first insulating film, a semiconductor layer, and a second insulating film in this order.Type: GrantFiled: February 18, 2004Date of Patent: January 24, 2006Assignee: Hitachi, Ltd.Inventors: Tetsuya Kawamura, Takeshi Tanaka, Kikuo Ono, Masaaki Matsuda, Kouichi Anno, Hiroshi Okawara
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Publication number: 20050218402Abstract: A thin-film transistor substrate includes a pixel region where gate electrode lines are arranged on an insulating substrate sandwiching semiconductor layer patterns and a gate insulator with the insulating substrate, wherein shapes of the semiconductor patterns and the gate electrode lines are set so that a value of K obtained by the following equation is smaller than a first set value when the thin-film transistor substrate is mounted on a metal table: K=(L/Ce)×{Ca/(Ca+Cb)}×S where Ca represents a capacitor between each of the semiconductor layer patterns and the metal table, Cb represents a capacitor between each of the semiconductor layer patterns and the gate electrode lines, Ce represents a capacitor between each of the gate electrode lines and the metal table, L represents a length of each of the gate electrode line, and S represents a substrate surface area that one of the gate electrode lines are in charge of per unit length.Type: ApplicationFiled: March 21, 2005Publication date: October 6, 2005Applicant: TOSHIBA MATSUSHITA DISPLAY TECHNOLOGY CO., LTD.Inventors: Tetsuya Kawamura, Katsuhiko Inada
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Patent number: 6934000Abstract: At terminal portions, the occurrence of electrolytic corrosion can be suppressed and, at the same time, the connection resistance between the terminal portions and other electrodes to be connected is largely reduced. On a liquid-crystal-side surface of one substrate out of a pair of substrates which are arranged to face each other by way of liquid crystal, signal lines, an insulation film covering the signal lines, terminal portions having one portions of the signal lines exposed by forming holes in the insulation film, and conductive oxide films laminated to the terminal portions are formed. The conductive oxide films are laminated to peripheries of the terminal portions except for the centers of the terminal portions.Type: GrantFiled: September 20, 2000Date of Patent: August 23, 2005Assignee: Hitachi, Ltd.Inventors: Masahiro Ishii, Tetsuya Kawamura, Hiroshi Yamate, Masaru Takabatake
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Publication number: 20050140570Abstract: Gate electrode lines 11 formed on glass substrate 3 are separated by separating portions 32 for respective pixels 5 to shorten lengths of gate electrode lines 11. Both end portions of gate electrode lines 11 separated by separating portions 32 are electrically connected by conductive films 42 made from the same materials as signal electrode lines 13. When glass substrate 3 is lifted up while glass substrate 3 is charged with static electricity, the increases in voltages at gate insulation film 31 provided between gate electrode lines 11 and polycrystalline semiconductor film 22 are effectively suppressed so that electrostatic destruction of gate electrode lines 11 can be prevented.Type: ApplicationFiled: October 21, 2004Publication date: June 30, 2005Applicant: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Hiroshi Tabatake, Tetsuya Kawamura, Shinichi Kawamura, Katsuhiko Inada, Atsushi Takeda, Nobuo Imai, Akihiro Takami
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Publication number: 20050127358Abstract: Dummy holes 36 are made for every one of display dot 5a, 5b and 5c at pixels 5 through interlayer film 33 up to gate electrode and scanning lines 11 before interlayer film 33 on glass substrate 3 is washed. When interlayer film 33 is washed, electric charges stored at semiconductor layer 21 are substantially the same in quantity as those stored at gate electrode and scanning lines 11 through dummy holes 36. Thus, electric potentials at gate electrode and scanning lines 11 are substantially equal in magnitude to those at semiconductor layer 21. This can suppress the occurrence of voltage differences imposed between gate electrode and scanning lines 11 and semiconductor layer 21.Type: ApplicationFiled: November 29, 2004Publication date: June 16, 2005Applicant: Toshiba Matsushita Display Technology Co., LtdInventor: Tetsuya Kawamura
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Publication number: 20050046773Abstract: A liquid crystal display device comprising a pair of substrates with liquid crystal layer therebetween, a plurality of gate signal lines and a plurality of drain signal lines formed on one of the pair of substrates, at least a pixel electrode and a plurality of counter electrodes formed on the one of the pair of substrates in each pixels, at least one of the plurality of counter electrodes extend along a drain signal line overlaqpping to the drain signal lines with at least one of an insulation film therebetween, and the drain signal line has two or more regions which differ in distance between a surface of the drain signal line and the counter electrode.Type: ApplicationFiled: October 14, 2004Publication date: March 3, 2005Inventors: Yoshiaki Nakayoshi, Nagatoshi Kurahashi, Tetsuya Kawamura, Kazuhiko Yanagawa
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Publication number: 20050042817Abstract: Poly-silicon semiconductor layer 21 and dummy poly-silicon semiconductor layer 25 are formed in insulation from each other on glass substrate 3. Gate insulation film 31 is formed on poly-silicon semiconductor layer 21, dummy poly-silicon semiconductor layer 25 and glass substrate 3. Gate insulation film 31 is covered with scanning and gate lines 11, which is overlapped with poly-silicon semiconductor layer 21 and dummy poly-silicon semiconductor layer 25. Poly-silicon semiconductor layer 21 is coupled with scanning and gate line 11 to define capacitors Ca and is also coupled with a reference potential to define capacitor Cb. Likewise, dummy poly-silicon semiconductor layer 25 is coupled with scanning and gate line 11 to define capacitors Cc and is also coupled with a reference potential to define capacitor Cd.Type: ApplicationFiled: August 5, 2004Publication date: February 24, 2005Applicant: Toshiba Matsushita Display Technology Co., Ltd.Inventor: Tetsuya Kawamura
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Patent number: 6842164Abstract: In a liquid crystal display comprising a plurality of pixels each of which has an switching element, a plurality of drain drivers and gate drivers for operating the switching elements and the pixels, and a plurality of drain lines and gate lines supplying signals from the drain drivers and the gate drivers to the switching elements being formed on one of a pair of substrates sandwiching a liquid crystal layer, the present invention provides wiring lines formed on the one of a pair of substrates for transferring display data signals and a clock signal between each pair of the plurality of drain drivers adjacent to one another, and provides at least one gate circuit for at least one of the plurality of drain drivers which is controlled by the clock signal and switches the display data signals and the clock signal either (1) to be acquired by the at least one of the plurality of drain drivers or (2) to be transferred to another of the plurality of drain drivers arranged adjacent to the at least one of the pluralType: GrantFiled: December 30, 2003Date of Patent: January 11, 2005Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Yoshihiro Imajo, Tetsuro Izawa, Kimitoshi Ohgiichi, Hiroshi Okawara, Shiro Ueda, Nobuyuki Ishige, Tetsuya Kawamura, Hisashi Ishino, Fumiaki Komori
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Patent number: 6836310Abstract: In a liquid crystal display device having a flexible printed circuit board which includes a laminated structure of a pair of flexible films, a plurality of first conductive layers interposed between inner surfaces of the flexible films to be spaced from each other, and a plurality of groups of terminals formed on an outer surface of one of flexible films opposite to the respective first conductive layers, and a liquid crystal display panel which includes a plurality of groups of wirings formed on one of a pair of substrates thereof and connected to the plurality of groups of terminals respectively, the present invention interposes second conductive layers at respective portions spacing the plurality of first conductive layers between the inner surfaces of the flexible films and prevents the one of the pair of substrates from being cracked when the plurality of terminals of the flexible printed circuit board are connected to the groups of wiring of the one of the substrates by compression bonding thereby.Type: GrantFiled: March 17, 2004Date of Patent: December 28, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroyuki Yamazaki, Tomio Oosone, Tetsuya Kawamura