Patents by Inventor Tetsuya Miyatake

Tetsuya Miyatake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094459
    Abstract: An optical waveguide includes a diamond layer including a first surface, a second surface and a diamond layer including a complex defect; a first clad layer in contact with the first surface; a second clad layer in contact with the second surface and including a polarity; and a metal layer in Schottky contact with the second clad layer.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro ISHIGURO, Tetsuya MIYATAKE, Kenichi KAWAGUCHI, Toshiki IWAI, Yoshiyasu DOI, Shintaro SATO
  • Publication number: 20230280528
    Abstract: A method of manufacturing a quantum circuit, the method includes forming, in a diamond layer that includes a color center, an optical waveguide optically coupled the color center, the diamond layer having a first principal surface and a second principal surface, wherein the optical waveguide includes: a core region that includes the color center; and an optical confinement region provided around the core region, a refractive index of the optical confinement region is lower than the refractive index of the core region.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 7, 2023
    Applicant: Fujitsu Limited
    Inventor: Tetsuya MIYATAKE
  • Publication number: 20230222375
    Abstract: A quantum circuit includes a plurality of first optical waveguides and a plurality of second optical waveguides formed on a substrate and each of which includes a single-photon source; a first multiplexer formed on the substrate and configured to condense first photons propagated through the plurality of first optical waveguides; a second multiplexer formed on the substrate and configured to condense second photons propagated through the plurality of second optical waveguides; a branching element configured to introduce the first photons condensed by the first multiplexer and the second photons condensed by the second multiplexer and branch the first photons and the second photons in a first direction and a second direction; a first detector configured to detect the first photons and the second photons branched in the first direction; and a second detector configured to detect the first photons and the second photons branched in the second direction.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro ISHIGURO, Kenichi KAWAGUCHI, Toshiyuki MIYAZAWA, Toshiki IWAI, Tetsuya MIYATAKE, Yoshiyasu DOI, Shintaro SATO
  • Patent number: 10187713
    Abstract: A main body case 9 includes an output opening 43 for outputting sound from a sound source to an opposing space between an upper main wall 33 and a lower main wall 34. The main body case 9 includes a front main wall 41 for preventing entering of a water droplet to the output opening 43 and for guiding the sound to a rear side B, and a rear main wall 35 for reflecting the sound to a front side F. A first space 51 between the front main wall 41 and the rear main wall 35, a second space 52 surrounded by a left surface 41C of the front main wall 41 and the rear main wall 35 and the upper main wall 33 and the lower main wall 34 and a third space 53 surrounded by a right surface 41D the front main wall 41 and the rear main wall 35 and the upper main wall 33 and the lower main wall 34 are communicating with one another along a crosswise direction Y at a rear end part of each of these spaces.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 22, 2019
    Assignee: Patlite Corporation
    Inventors: Tetsuya Miyatake, Kazuya Nishimatsu, Yusuke Tone, Daisuke Shigematsu
  • Patent number: 9883269
    Abstract: A main body case 9 includes an output opening 43 for outputting sound from a sound source to an opposing space between an upper main wall 33 and a lower main wall 34. The main body case 9 includes a front main wall 41 for preventing entering of a water droplet to the output opening 43 and for guiding the sound to a rear side B, and a rear main wall 35 for reflecting the sound to a front side F. A first space 51 between the front main wall 41 and the rear main wall 35, a second space 52 surrounded by a left surface 41C of the front main wall 41 and the rear main wall 35 and the upper main wall 33 and the lower main wall 34 and a third space 53 surrounded by a right surface 41D the front main wall 41 and the rear main wall 35 and the upper main wall 33 and the lower main wall 34 are communicating with one another along a crosswise direction Y at a rear end part of each of these spaces.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 30, 2018
    Assignee: PATLITE CORPORATION
    Inventors: Tetsuya Miyatake, Kazuya Nishimatsu, Yusuke Tone, Daisuke Shigematsu
  • Publication number: 20170134838
    Abstract: A main body case 9 includes an output opening 43 for outputting sound from a sound source to an opposing space between an upper main wall 33 and a lower main wall 34. The main body case 9 includes a front main wall 41 for preventing entering of a water droplet to the output opening 43 and for guiding the sound to a rear side B, and a rear main wall 35 for reflecting the sound to a front side F. A first space 51 between the front main wall 41 and the rear main wall 35, a second space 52 surrounded by a left surface 41C of the front main wall 41 and the rear main wall 35 and the upper main wall 33 and the lower main wall 34 and a third space 53 surrounded by a right surface 41D the front main wall 41 and the rear main wall 35 and the upper main wall 33 and the lower main wall 34 are communicating with one another along a crosswise direction Y at a rear end part of each of these spaces.
    Type: Application
    Filed: February 18, 2015
    Publication date: May 11, 2017
    Inventors: Tetsuya MIYATAKE, Kazuya NISHIMATSU, Yusuke TONE, Daisuke SHIGEMATSU
  • Patent number: 9243952
    Abstract: An apparatus includes a flip-chip semiconductor substrate, a light detection element configured to be formed over the flip-chip semiconductor substrate and to have a laminate structure including a first semiconductor layer of a first-conductive-type, a light-absorption layer formed over the first semiconductor layer, and a second semiconductor layer of a second-conductive-type formed over the light-absorption layer, an inductor configured to be connected to the light detection element over the flip-chip semiconductor substrate, an output electrode for bump connection configured to output a current generated by the light detection element through the inductor, a bias electrode for bump connection configured to apply a bias voltage to the light detection element through a bias electrode, and a line configured to cause a metal line of the inductor and the light detection element to be connected to the output electrode or the bias electrode.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: January 26, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Tetsuya Miyatake
  • Publication number: 20140231628
    Abstract: An apparatus includes a flip-chip semiconductor substrate, a light detection element configured to be formed over the flip-chip semiconductor substrate and to have a laminate structure including a first semiconductor layer of a first-conductive-type, a light-absorption layer formed over the first semiconductor layer, and a second semiconductor layer of a second-conductive-type formed over the light-absorption layer, an inductor configured to be connected to the light detection element over the flip-chip semiconductor substrate, an output electrode for bump connection configured to output a current generated by the light detection element through the inductor, a bias electrode for bump connection configured to apply a bias voltage to the light detection element through a bias electrode, and a line configured to cause a metal line of the inductor and the light detection element to be connected to the output electrode or the bias electrode.
    Type: Application
    Filed: April 23, 2014
    Publication date: August 21, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuya Miyatake
  • Patent number: 8805127
    Abstract: An optical waveguide device includes: a substrate which has an electro-optical effect; an optical waveguide which is formed on the substrate and/or inside the substrate; and an in-substrate electrode which is formed of a metal and provided inside the substrate.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: August 12, 2014
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Miyatake, Takashi Shiraishi, Masaharu Doi
  • Patent number: 8783971
    Abstract: An optical transmission apparatus comprising a first gradient index lens, an optical receiver, and a second gradient index lens. The first gradient index lens is connected to an end of an optical transmission line. The optical receiver receives light and is provided to an electronic device. The second gradient index lens is arranged between the first gradient index lens and the optical receiver.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: July 22, 2014
    Assignee: Fujitsu Limited
    Inventor: Tetsuya Miyatake
  • Patent number: 8766390
    Abstract: An apparatus includes a flip-chip semiconductor substrate, a light detection element configured to be formed over the flip-chip semiconductor substrate and to have a laminate structure including a first semiconductor layer of a first-conductive-type, a light-absorption layer formed over the first semiconductor layer, and a second semiconductor layer of a second-conductive-type formed over the light-absorption layer, an inductor configured to be connected to the light detection element over the flip-chip semiconductor substrate, an output electrode for bump connection configured to output a current generated by the light detection element through the inductor, a bias electrode for bump connection configured to apply a bias voltage to the light detection element through a bias electrode, and a line configured to cause a metal line of the inductor and the light detection element to be connected to the output electrode or the bias electrode.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: July 1, 2014
    Assignee: Fujitsu Limited
    Inventor: Tetsuya Miyatake
  • Publication number: 20140034602
    Abstract: An optical waveguide device includes: a substrate which has an electro-optical effect; an optical waveguide which is formed on the substrate and/or inside the substrate; and an in-substrate electrode which is formed of a metal and provided inside the substrate.
    Type: Application
    Filed: October 10, 2013
    Publication date: February 6, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuya MIYATAKE, Takashi SHIRAISHI, Masaharu DOI
  • Patent number: 8582928
    Abstract: An optical waveguide device includes: a substrate which has an electro-optical effect; an optical waveguide which is formed on the substrate and/or inside the substrate; and an in-substrate electrode which is formed of a metal and provided inside the substrate.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Miyatake, Takashi Shiraishi, Masaharu Doi
  • Publication number: 20130094224
    Abstract: A light emitting apparatus includes a light-transmissive cover including a pair of side walls, a heat dissipation member including a pair of outer surfaces disposed between inner surfaces of the pair of side walls of the cover and including a fin disposed between the outer surfaces, a light emitting element supported by the heat dissipation member and accommodated in the cover, projections, and recesses. One of the cover and the heat dissipation member has the projections, which are respectively provided on the inner surfaces of the cover or the outer surfaces of the heat dissipation member. The other of the cover and the heat dissipation member has the recesses, which are respectively provided on the inner surfaces of the cover or the outer surfaces of the heat dissipation member. The recesses extend longitudinally of the cover in engagement with the respective projections.
    Type: Application
    Filed: October 26, 2012
    Publication date: April 18, 2013
    Inventors: Tetsuya Miyatake, Koichi Hazumi
  • Publication number: 20120313210
    Abstract: An apparatus includes a flip-chip semiconductor substrate, a light detection element configured to be formed over the flip-chip semiconductor substrate and to have a laminate structure including a first semiconductor layer of a first-conductive-type, a light-absorption layer formed over the first semiconductor layer, and a second semiconductor layer of a second-conductive-type formed over the light-absorption layer, an inductor configured to be connected to the light detection element over the flip-chip semiconductor substrate, an output electrode for bump connection configured to output a current generated by the light detection element through the inductor, a bias electrode for bump connection configured to apply a bias voltage to the light detection element through a bias electrode, and a line configured to cause a metal line of the inductor and the light detection element to be connected to the output electrode or the bias electrode.
    Type: Application
    Filed: April 4, 2012
    Publication date: December 13, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuya Miyatake
  • Patent number: D681261
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: April 30, 2013
    Assignee: Patlite Corporation
    Inventors: Tetsuya Miyatake, Koichi Hazumi
  • Patent number: D695951
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 17, 2013
    Assignee: Patlite Corporation
    Inventors: Tetsuya Miyatake, Koichi Hazumi
  • Patent number: D718891
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 2, 2014
    Assignee: Patlite Corporation
    Inventors: Kaoru Sawano, Keiko Uemura, Tetsuya Miyatake
  • Patent number: D791630
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: July 11, 2017
    Assignee: PATLITE CORPORATION
    Inventors: Tetsuya Miyatake, Keiko Uemura
  • Patent number: D1027040
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: May 14, 2024
    Assignee: Nintendo Co., Ltd.
    Inventors: Yui Ehara, Yuko Zenri, Junichiro Miyatake, Tetsuya Akama, Hitoshi Tsuchiya