Patents by Inventor Tetsuya Mochida
Tetsuya Mochida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100306438Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: ApplicationFiled: August 13, 2010Publication date: December 2, 2010Applicant: HITACHI, LTD.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7802045Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: July 13, 2009Date of Patent: September 21, 2010Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20090276557Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween.Type: ApplicationFiled: July 13, 2009Publication date: November 5, 2009Applicant: HITACHI, LTD.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7577781Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: May 29, 2008Date of Patent: August 18, 2009Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20080244124Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween.Type: ApplicationFiled: May 29, 2008Publication date: October 2, 2008Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7398346Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: October 6, 2006Date of Patent: July 8, 2008Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20080063244Abstract: A biometric apparatus is provided that comprises a personal computer (PC), and a finger vein authentication module connected to the PC, wherein the PC retrieves finger vein position information of an organism from a biometric image obtained during registration of a user for displaying on the screen of a liquid crystal display during authentication, and superimposes current finger contour information obtained during the authentication on the finger contour position information for displaying on the screen of the liquid crystal display. With this, even when the biometric apparatus is not provided with a jig that fixes the organism, it is possible, during the authentication, to cause the organism to match the position and angle a template captured during registration, and to complete the authentication rapidly.Type: ApplicationFiled: September 13, 2007Publication date: March 13, 2008Inventors: Yuichiro Tanaka, Tetsuya Mochida, Harumi Sato
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Patent number: 7340552Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: December 21, 2006Date of Patent: March 4, 2008Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Publication number: 20070106832Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: ApplicationFiled: December 21, 2006Publication date: May 10, 2007Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 7177970Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: October 22, 2002Date of Patent: February 13, 2007Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Publication number: 20070033316Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: ApplicationFiled: October 6, 2006Publication date: February 8, 2007Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7152130Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: January 11, 2005Date of Patent: December 19, 2006Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 6907489Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: February 27, 2004Date of Patent: June 14, 2005Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20050125585Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: ApplicationFiled: January 11, 2005Publication date: June 9, 2005Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 6810461Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: October 24, 2001Date of Patent: October 26, 2004Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20040168007Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: ApplicationFiled: February 27, 2004Publication date: August 26, 2004Applicant: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 6728258Abstract: In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.Type: GrantFiled: December 8, 1999Date of Patent: April 27, 2004Assignee: Hitachi, Ltd.Inventors: Tetsuhiko Okada, Naoki Hamanaka, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida, Masabumi Shibata, Youichi Tanaka, Yasuhiro Ishii
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Publication number: 20030070020Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: ApplicationFiled: October 22, 2002Publication date: April 10, 2003Applicant: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 6519667Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: November 26, 2001Date of Patent: February 11, 2003Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Publication number: 20020065972Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: ApplicationFiled: October 24, 2001Publication date: May 30, 2002Applicant: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida