Patents by Inventor Tetsuya Mochida
Tetsuya Mochida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020032817Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: ApplicationFiled: November 26, 2001Publication date: March 14, 2002Applicant: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 6341323Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: February 7, 2001Date of Patent: January 22, 2002Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 6334164Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: October 18, 2000Date of Patent: December 25, 2001Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20010023462Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: ApplicationFiled: February 7, 2001Publication date: September 20, 2001Applicant: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 6219738Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: February 28, 2000Date of Patent: April 17, 2001Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 6195719Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and controL buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: March 3, 2000Date of Patent: February 27, 2001Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 6128688Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: April 23, 1999Date of Patent: October 3, 2000Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 6098136Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controlling connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: August 17, 1999Date of Patent: August 1, 2000Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 6078944Abstract: The parallelism of execution of processes in a memory shared multi-processor is enhanced. Each of a plurality of processors is provided with a run queue for holding executable processes, and a watch process for each processor to watch the execution status of its own to notify the rebuilding of the run queue to other processor and a rebuild step for rebuilding the run queue in response to the notice are stored in a shared memory as a program.Type: GrantFiled: April 1, 1997Date of Patent: June 20, 2000Assignee: Hitachi, Ltd.Inventors: Yutaka Enko, Toshiaki Arai, Reki Yamamoto, Naofumi Shouji, Tomoki Sekiguchi, Tsutomu Noda, Tsuyoshi Watanabe, Tetsuya Mochida
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Patent number: 6011791Abstract: In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.Type: GrantFiled: November 12, 1996Date of Patent: January 4, 2000Assignee: Hitachi, Ltd.Inventors: Tetsuhiko Okada, Naoki Hamanaka, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida, Masabumi Shibata, Youichi Tanaka, Yasuhiro Ishii
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Patent number: 6006302Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: March 26, 1999Date of Patent: December 21, 1999Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Bus control system incorporating the coupling of two split-transaction busses of different hierarchy
Patent number: 5941973Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: December 1, 1998Date of Patent: August 24, 1999Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi -
Patent number: 5935231Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: August 31, 1998Date of Patent: August 10, 1999Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 5890220Abstract: In a computer system having an address converter for DMA (direct memory access), an address conversion apparatus in which a memory area to be accessed by the DMA can be accessed at high speed from a CPU. A "DMA address conversion area" is defined in a memory space, and address conversion means in the mode of accessing the DMA address conversion area is so constructed that, when the area has been accessed from the CPU, a physical address is generated in accordance with the address conversion routine of the DMA address conversion means or converter, so as to access a main storage. The memory area to be accessed by the DMA can be quickly accessed from the CPU without requiring such an operation as especially accessing the control ware of the address converter or producing the physical address under the management of a program run on the CPU.Type: GrantFiled: May 31, 1995Date of Patent: March 30, 1999Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.Inventors: Tetsuya Mochida, Hitoshi Kawaguchi, Kazushi Kobayashi, Ichiharu Aburano, Takanori Ishikawa
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Patent number: 5889971Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: October 29, 1997Date of Patent: March 30, 1999Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Bus control system incorporating the coupling of two split-transaction busses of different hierarchy
Patent number: 5881255Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: April 21, 1997Date of Patent: March 9, 1999Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi -
Patent number: 5751976Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: February 15, 1996Date of Patent: May 12, 1998Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 5671371Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: October 18, 1995Date of Patent: September 23, 1997Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 5668956Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: May 24, 1995Date of Patent: September 16, 1997Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 5506973Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: May 17, 1995Date of Patent: April 9, 1996Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida