Abstract: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer.

Abstract: A semiconductor device includes an N-channel transistor having an N-type gate electrode and a P-channel transistor having a P-type gate electrode which are formed on a semiconductor substrate. The P-type gate electrode includes a first silicon layer formed as the lowest layer, and doped with a P-type impurity; a second silicon layer formed on the first silicon layer; and a metal containing layer formed on the second silicon layer. The N-type gate electrode includes a third silicon layer formed as the lowest layer and doped with an N-type impurity; a fourth silicon layer formed on the third silicon layer; and a metal containing layer formed on the fourth silicon layer. At least one of the second silicon layer and the fourth silicon layer is doped with no impurity or an impurity of a conductive type opposite to that of the impurity in a corresponding one of the first silicon layer and third silicon layer.

Abstract: Method for manufacturing a semiconductor device including a transistor having a grooved gate structure and a transistor having a planar gate structure on the same substrate, in which, even when the semiconductor device is configured as a dual gate structure in which a gate electrode structure is a poly-metal gate structure, and a grooved gate and a planar gate are made in different conductivity types, then sufficient dopant is injected into polysilicon in the grooved gate to prevent depletion, and impurity ions do not pass through a gate insulating film even when the planar gate is formed also polysilicon having the same film thickness. The method includes: injecting ions into an amorphous silicon layer for the grooved gate; subsequently, turning it into polysilicon once; injecting ions once again to amorphousize a surface layer of the polysilicon layer and injecting ions of a different conductivity type for the planar gate.

Abstract: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer.

Abstract: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer.

Abstract: Method for manufacturing a semiconductor device including a transistor having a grooved gate structure and a transistor having a planar gate structure on the same substrate, in which, even when the semiconductor device is configured as a dual gate structure in which a gate electrode structure is a poly-metal gate structure, and a grooved gate and a planar gate are made in different conductivity types, then sufficient dopant is injected into polysilicon in the grooved gate to prevent depletion, and impurity ions do not pass through a gate insulating film even when the planar gate is formed also polysilicon having the same film thickness. The method includes: injecting ions into an amorphous silicon layer for the grooved gate; subsequently, turning it into polysilicon once; injecting ions once again to amorphousize a surface layer of the polysilicon layer and injecting ions of a different conductivity type for the planar gate.

Abstract: A semiconductor device includes an N-channel transistor having an N-type gate electrode and a P-channel transistor having a P-type gate electrode which are formed on a semiconductor substrate. The P-type gate electrode includes a first silicon layer formed as the lowest layer, and doped with a P-type impurity; a second silicon layer formed on the first silicon layer; and a metal containing layer formed on the second silicon layer. The N-type gate electrode includes a third silicon layer formed as the lowest layer and doped with an N-type impurity; a fourth silicon layer formed on the third silicon layer; and a metal containing layer formed on the fourth silicon layer. At least one of the second silicon layer and the fourth silicon layer is doped with no impurity or an impurity of a conductive type opposite to that of the impurity in a corresponding one of the first silicon layer and third silicon layer.

Abstract: A semiconductor device includes a gate electrode including a polysilicon layer, a tungsten silicide layer, a tungsten nitride layer, and a tungsten layer, which are arranged in this order as viewed from a silicon substrate. The polysilicon layer is doped with phosphor, and the tungsten silicide layer is doped with nitrogen. The polysilicon layer is additionally doped with nitrogen in the top portion thereof.

Abstract: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer.

Abstract: A gate electrode structure in a semiconductor device has a doped polysilicon (DOPOS) film, a tungsten silicide film, a tungsten silicide nitride film, a tungsten nitride film and a tungsten film consecutively as viewed from the substrate. The tungsten silicide nitride film is formed between the tungsten silicide film and the tungsten nitride film by a plurality of heat treatments. The tungsten silicide nitride film has a small thickness of 2 to 5 nm and has a lower interface resistance for achieving a low-resistance gate electrode, suited for a higher-speed operation of the semiconductor device.

Abstract: A semiconductor device has a dual-gate electrode structure. The gate electrode has a layered structure including a doped polysilicon film, WSi2 film, WN film and a W film. The WSi2 film formed on the polysilicon film in the P-channel area is formed of a number of WSi2 particles disposed apart from one another, preventing a bilateral diffusion of impurities doped in the polysilicon film.

Abstract: A semiconductor device has a dual-gate electrode structure. The gate electrode has a layered structure including a doped polysilicon film, WSi2 film, WN film and a W film. The WSi2 film formed on the polysilicon film in the P-channel area is formed of a number of WSi2 particles disposed apart from one another, preventing a bilateral diffusion of impurities doped in the polysilicon film.

Abstract: A gate electrode structure in a semiconductor device has a doped polysilicon (DOPOS) film, a tungsten silicide film, a tungsten silicide nitride film, a tungsten nitride film and a tungsten film consecutively as viewed from the substrate. The tungsten silicide nitride film is formed between the tungsten silicide film and the tungsten nitride film by a plurality of heat treatments. The tungsten silicide nitride film has a small thickness of 2 to 5 nm and has a lower interface resistance for achieving a low-resistance gate electrode, suited for a higher-speed operation of the semiconductor device.

Abstract: A gate electrode structure in a semiconductor device has a doped polysilicon (DOPOS) film, a tungsten silicide film, a tungsten silicide nitride film, a tungsten nitride film and a tungsten film consecutively as viewed from the substrate. The tungsten silicide nitride film is formed between the tungsten silicide film and the tungsten nitride film by a plurality of heat treatments. The tungsten silicide nitride film has a small thickness of 2 to 5 nm and has a lower interface resistance for achieving a low-resistance gate electrode, suited for a higher-speed operation of the semiconductor device.

Abstract: A processed object, i.e., a circuit-constituting member is positioned by a member-transferring unit at a given position in a member-waiting portion when plasma starts to be generated in a plasma-generative portion, and the circuit-constituting member is transferred from the member-waiting portion to the plasma-generative portion when the plasma started to be generated in the plasma-generative portion is brought into a stable condition thereof. Thus, the circuit-constituting member is not subjected to a circuit-processing by plasma before the stable condition is not reached but is surely subjected to the circuit-processing-only by plasma in the stable condition.

Abstract: There is disclosed a process for manufacturing a semiconductor device. When a metal film is formed by plasma CVD in a contact hole which penetrates an interlayer insulating film and reaches an electrode of the device, a gas comprising hydrogen and argon in a deposition chamber of a plasma CVD apparatus is introduced. Then a metal halide gas is introduced in the deposition chamber simultaneously with or before plasma generation.

Abstract: A barrier metal that can be used in a semiconductor is to be made extremely thin. Further, the manufacturing steps of a semiconductor device are shortened to reduce its manufacturing cost. An insulating layer (e.g., a thermal nitride layer 10) with good step coverage formed on a surface of a conductor film such as lower electrodes 9 and 9a of a capacitor on a semiconductor substrate is transformed into a reformed layer 11, which serves as a conductive barrier layer. Alternatively, the insulating layer formed on the surface of the insulating layer on the semiconductor substrate is totally or partially reformed into the conductive barrier layer. This reforming process is conducted by heating the above-mentioned semiconductor substrate at a predetermined temperature and, applying a plasma-excited high melting-point metal onto the surface of the above-mentioned insulating layer. This high melting-point metal may be Ti, Ta, Ni, Mo, W or the like.

Abstract: A processed object, i.e., a circuit-constituting member is positioned by a member-transferring unit at a given position in a member-waiting portion when plasma starts to be generated in a plasma-generative portion, and the circuit-constituting member is transferred from the member-waiting portion to the plasma-generative portion when the plasma started to be generated in the plasma-generative portion is brought into a stable condition thereof. Thus, the circuit-constituting member is not subjected to a circuit-processing by plasma before the stable condition is not reached but is surely subjected to the circuit-processing only by plasma in the stable condition.

Abstract: A gate electrode structure in a semiconductor device has a doped polysilicon (DOPOS) film, a tungsten silicide film, a tungsten silicide nitride film, a tungsten nitride film and a tungsten film consecutively as viewed from the substrate. The tungsten silicide nitride film is formed between the tungsten silicide film and the tungsten nitride film by a plurality of heat treatments. The tungsten silicide nitride film has a small thickness of 2 to 5 nm and has a lower interface resistance for achieving a low-resistance gate electrode, suited for a higher-speed operation of the semiconductor device.

Abstract: A barrier metal that can be used in a semiconductor is to be made extremely thin. Further, the manufacturing steps of a semiconductor device are shortened to reduce its manufacturing cost. An insulating layer (e.g., a thermal nitride layer 10) with good step coverage formed on a surface of a conductor film such as lower electrodes 9 and 9a of a capacitor on a semiconductor substrate is transformed into a reformed layer 11, which serves as a conductive barrier layer. Alternatively, the insulating layer formed on the surface of the insulating layer on the semiconductor substrate is totally or partially reformed into the conductive barrier layer. This reforming process is conducted by heating the above-mentioned semiconductor substrate at a predetermined temperature and, applying a plasma-excited high melting-point metal onto the surface of the above-mentioned insulating layer. This high melting-point metal may be Ti, Ta, Ni, Mo, W or the like.