Patents by Inventor Tetsuya Tateno
Tetsuya Tateno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8100496Abstract: An ink tank receives data signals from a printer and an LED provided on the ink tank is driven on the basis of the received data signals. The LED is driven in an inactive time period that is different from the time period in which the date signals are input to the ink tank.Type: GrantFiled: October 21, 2010Date of Patent: January 24, 2012Assignee: Canon Kabushiki KaishaInventors: Nobuyuki Hatasa, Kenjiro Watanabe, Kimiyuki Hayasaki, Tatsuhiko Yamazaki, Tetsuya Tateno
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Publication number: 20110032317Abstract: An ink tank receives data signals from a printer and an LED provided on the ink tank is driven on the basis of the received data signals. The LED is driven in an inactive time period that is different from the time period in which the date signals are input to the ink tank.Type: ApplicationFiled: October 21, 2010Publication date: February 10, 2011Applicant: Canon Kabushiki KaishaInventors: Nobuyuki Hatasa, Kenjiro Watanabe, Kimiyuki Hayasaki, Tatsuhiko Yamazaki, Tetsuya Tateno
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Patent number: 7841681Abstract: An ink tank receives data signals from a printer and an LED provided on the ink tank is driven on the basis of the received data signals. The LED is driven in an inactive time period that is different from the time period in which the date signals are input to the ink tank.Type: GrantFiled: July 22, 2008Date of Patent: November 30, 2010Assignee: Canon Kabushiki KaishaInventors: Nobuyuki Hatasa, Kenjiro Watanabe, Kimiyuki Hayasaki, Tatsuhiko Yamazaki, Tetsuya Tateno
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Publication number: 20080278081Abstract: An ink tank receives data signals from a printer and an LED provided on the ink tank is driven on the basis of the received data signals. The LED is driven in an inactive time period that is different from the time period in which the date signals are input to the ink tank.Type: ApplicationFiled: July 22, 2008Publication date: November 13, 2008Applicant: CANON KABUSHIKI KAISHAInventors: Nobuyuki Hatasa, Kenjiro Watanabe, Kimiyuki Hayasaki, Tatsuhiko Yamazaki, Tetsuya Tateno
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Patent number: 7448712Abstract: An ink tank receives data signals from a printer and an LED provided on the ink tank is driven on the basis of the received data signals. The LED is driven in an inactive time period that is different from the time period in which the date signals are input to the ink tank.Type: GrantFiled: June 7, 2006Date of Patent: November 11, 2008Assignee: Canon Kabushiki KaishaInventors: Nobuyuki Hatasa, Kenjiro Watanabe, Kimiyuki Hayasaki, Tatsuhiko Yamazaki, Tetsuya Tateno
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Patent number: 7328288Abstract: In order to reduce overhead of a CPU, a relay apparatus for relaying communication from a CPU to a peripheral device includes communication information holding sections for holding information required for communication with the peripheral devices inside the relay apparatus; and command holding sections, which are provided adjacent to the communication information holding section, for holding commands used to communicate desired information inside the communication information holding section to the peripheral device. The CPU writes desired information in the communication information holding section and the command holding section inside the relay apparatus by burst-mode communication, and the relay apparatus performs communication with the peripheral devices in accordance with instructions from the command holding section after the writing of the desired information in the communication holding section and the command holding section is completed.Type: GrantFiled: December 3, 2004Date of Patent: February 5, 2008Assignee: Canon Kabushiki KaishaInventor: Tetsuya Tateno
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Patent number: 7218788Abstract: In image data coding and decoding processing, in order to improve efficiency by processing a plurality of factors in one cycle as long as possible, the factors are rearranged, in coding or decoding processing, in a predetermined scan sequence such that significant factors and 0s are paired. In addition, an appropriate scan sequence is selected in accordance with the distribution state of frequencies to further improve the efficiency.Type: GrantFiled: February 12, 2002Date of Patent: May 15, 2007Assignee: Canon Kabushiki KaishaInventors: Susumu Igarashi, Tetsuya Tateno, Makoto Satoh, Yukio Chiba, Katsumi Otsuka
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Publication number: 20060290729Abstract: An ink tank receives data signals from a printer and an LED provided on the ink tank is driven on the basis of the received data signals. The LED is driven in an inactive time period that is different from the time period in which the date signals are input to the ink tank.Type: ApplicationFiled: June 7, 2006Publication date: December 28, 2006Applicant: Canon Kabushiki KaishaInventors: Nobuyuki Hatasa, Kenjiro Watanabe, Kimiyuki Hayasaki, Tatsuhiko Yamazaki, Tetsuya Tateno
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Decoding apparatus, method, and storage medium for inputting and decoding variable-length coded data
Patent number: 6993202Abstract: A decoding apparatus has: M tables for storing, in correspondence with M types of variable-length code tables, minimum code words or maximum code words of classes of variable-length code words constructing a variable-length code table; a table selector which selects one table from the M tables; N comparators which compare input coded data with the minimum code words or maximum code words outputted from the table selected by the table selector; a switch circuit and a priority encoder which obtain a class number corresponding to an initial code word of the input coded data based on results of comparison by the N comparators; a code length converter which converts the class number into a code length; and an address generator which generates an address to access a memory holding decoded data from the class number and the code length outputted said code length converter. The data outputted from the memory based on the address becomes decoded data of the input coded data.Type: GrantFiled: February 26, 2002Date of Patent: January 31, 2006Assignee: Canon Kabushiki KaishaInventors: Susumu Igarashi, Tetsuya Tateno, Makoto Sato, Yukio Chiba, Katsumi Otsuka -
Patent number: 6947602Abstract: Whether a header information processor quickly enters a program inactive state at the timing when it issues an operation start command of an encoding process for a predetermined processing unit to a variable-length code encoder, or the header information processor enters the program inactive state upon completion of execution steps to be processed is adaptively selected in accordance with the number of execution steps. One memory is shared by the header information processor and variable-length code encoder, and address input permission means for controlling to grant permission of an address input to the memory to one of the header information processor and the variable-length code encoder is provided. The memory is used as a work area of the header information processor, and as a storage area of a variable-length code table which is looked up by the variable-length code encoder.Type: GrantFiled: December 19, 2001Date of Patent: September 20, 2005Assignee: Canon Kabushiki KaishaInventors: Susumu Igarashi, Tetsuya Tateno, Makoto Satoh, Yukio Chiba, Katsumi Otsuka
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Publication number: 20050132098Abstract: In order to reduce overhead of a CPU, a relay apparatus for relaying communication from a CPU to a peripheral device includes communication information holding sections for holding information required for communication with the peripheral devices inside the relay apparatus; and command holding sections, which are provided adjacent to the communication information holding section, for holding commands used to communicate desired information inside the communication information holding section to the peripheral device. The CPU writes desired information in the communication information holding section and the command holding section inside the relay apparatus by burst-mode communication, and the relay apparatus performs communication with the peripheral devices in accordance with instructions from the command holding section after the writing of the desired information in the communication holding section and the command holding section is completed.Type: ApplicationFiled: December 3, 2004Publication date: June 16, 2005Applicant: Canon Kabushiki KaishaInventors: Kazuhiro Sonoda, Kazunari Kitani, Tetsuya Tateno
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Patent number: 6603413Abstract: This invention implements a variable-length code pipeline decoding process as hardware by providing additional bit processing means, reducing the load on external control, and clarifying encoded data shift means. For this purpose, in order to determine a code length and additional bit length, two different decode processes are executed, the overall process is separated into three stages, i.e., a stage for shifting out a code word of encoded data, a decode processing stage, and a symbol determination & additional bit processing stage, and these stages are executed in a pipeline manner.Type: GrantFiled: February 7, 2002Date of Patent: August 5, 2003Assignee: Canon Kabushiki KaishaInventors: Susumu Igarashi, Tetsuya Tateno, Makoto Satoh, Yukio Chiba, Katsumi Otsuka
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Publication number: 20020164080Abstract: A decoding apparatus has: M tables for storing, in correspondence with M types of variable-length code tables, minimum code words or maximum code words of classes of variable-length code words constructing a variable-length code table; a table selector which selects one table from the M tables; N comparators which compare input coded data with the minimum code words or maximum code words outputted from the table selected by the table selector; a switch circuit and a priority encoder which obtain a class number corresponding to an initial code word of the input coded data based on results of comparison by the N comparators; a code length converter which converts the class number into a code length; and an address generator which generates an address to access a memory holding decoded data from the class number and the code length outputted said code length converter. The data outputted from the memory based on the address becomes decoded data of the input coded data.Type: ApplicationFiled: February 26, 2002Publication date: November 7, 2002Applicant: CANON KABUSHI KAISHAInventors: Susumu Igarashi, Tetsuya Tateno, Makoto Sato, Yukio Chiba, Katsumi Otsuka
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Publication number: 20020154042Abstract: This invention implements a variable-length code pipeline decoding process as hardware by providing additional bit processing means, reducing the load on external control, and clarifying encoded data shift means.Type: ApplicationFiled: February 7, 2002Publication date: October 24, 2002Applicant: CANON KABUSHIKI KAISHAInventors: Susumu Igarashi, Tetsuya Tateno, Makoto Satoh, Yukio Chiba, Katsumi Otsuka
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Publication number: 20020122599Abstract: In image data coding and decoding processing, in order to improve efficiency by processing a plurality of factors in one cycle as long as possible, the factors are rearranged, in coding or decoding processing, in a predetermined scan sequence such that significant factors and 0s are paired. In addition, an appropriate scan sequence is selected in accordance with the distribution state of frequencies to further improve the efficiency.Type: ApplicationFiled: February 12, 2002Publication date: September 5, 2002Applicant: CANON KABUSHIKI KAISHAInventors: Susumu Igarashi, Tetsuya Tateno, Makoto Satoh, Yukio Chiba, Katsumi Otsuka
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Publication number: 20020090142Abstract: Whether a header information processor quickly enters a program inactive state at the timing when it issues an operation start command of an encoding process for a predetermined processing unit to a variable-length code encoder, or the header information processor enters the program inactive state upon completion of execution steps to be processed is adaptively selected in accordance with the number of execution steps. One memory is shared by the header information processor and variable-length code encoder, and address input permission means for controlling to grant permission of an address input to the memory to one of the header information processor and the variable-length code encoder is provided. The memory is used as a work area of the header information processor, and as a storage area of a variable-length code table which is looked up by the variable-length code encoder.Type: ApplicationFiled: December 19, 2001Publication date: July 11, 2002Inventors: Susumu Igarashi, Tetsuya Tateno, Makoto Satoh, Yukio Chiba, Katsumi Otsuka
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Patent number: 6313767Abstract: A decoding apparatus which efficiently stores information to determine an address value to read a decoded value from a decoded value memory. The apparatus performs decoding processing at a high speed, and further, reduces the memory capacity.Type: GrantFiled: February 14, 2000Date of Patent: November 6, 2001Assignee: Canon Kabushiki KaishaInventors: Keiji Ishizuka, Tetsuya Tateno, Koji Aoki
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Patent number: 5937146Abstract: A binarization processing apparatus for converting multi-value image data into binary image data is constructed by pixel groups in which pixels to be binarized are divided into a plurality of groups, a plurality of memories which correspond to the pixel groups and hold data in a binarization processing step, a control unit which performs the reading operation for one of the plurality of memories and simultaneously performs the writing operation for the other memory, and a unit for performing the converting process on the basis of an error diffusing method. The plurality of memories have a single common input/output port.Type: GrantFiled: August 30, 1996Date of Patent: August 10, 1999Assignee: Canon Kabushiki KaishaInventors: Tetsuya Tateno, Atsushi Furuya
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Patent number: 5751233Abstract: A decoder decodes input codes, such as Modified Huffman, Modified READ, and Modified Modified READ codes, and includes a zero bit detector which detects the number of consecutive leading zero bits of the input code. An address compressor forms address data by performing a logical operation of data indicating the number of detected zero bits and data excluding the consecutive leading zero bits and the next one bit of the data. A reference table for code conversion is addressed by the formed address data from the address compressor and outputs decoded data corresponding to the input code.Type: GrantFiled: May 10, 1996Date of Patent: May 12, 1998Assignee: Canon Kabushiki KaishaInventors: Tetsuya Tateno, Yuji Minami
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Patent number: 5448506Abstract: An operational circuit device for calculating a plurality of bit data includes, an input unit for inputting a plurality of bit data, a constant current source provided for each of the plurality of bit data for generating a predetermined current in accordance with the bit data inputted from the input unit and a calculation unit for calculating a sum of the predetermined currents from the constant current sources.Type: GrantFiled: April 1, 1994Date of Patent: September 5, 1995Assignee: Canon Kabushiki KaishaInventor: Tetsuya Tateno