Patents by Inventor Tetsuya Tateno

Tetsuya Tateno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4996443
    Abstract: An integrated circuit for level shift is a parallel-connected circuit comprised of a first circuit including a first MOS FET of one conductive type, a third MOS FET of another conductive type and a first MOS FET of the other conductive type which are series-connected in this order and a second circuit including a second MOS FET of the one conductive type, a fourth MOS FET of the other conductive type and a second MOS FET of the other conductive type which are series-connected in this order, wherein gates of the first and second MOS FETs of the one conductive type are connected respectively to the output side and input side of an inverter connected to a low voltage electric power source, gates of the third and fourth MOS FETs of the other conductive type both are connected to a reference voltage source, a gate of the first MOS FET of the other conductive type is connected to a common junction point of the fourth MOS FET and the second MOS FET of the other conductive type, a gate of the second MOS FET of the ot
    Type: Grant
    Filed: March 1, 1989
    Date of Patent: February 26, 1991
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tetsuya Tateno
  • Patent number: 4758820
    Abstract: A semiconductor circuit is provided with a constant current circuit, a resistor network to which a current from the constant current circuit is supplied, and a device between the constant current circuit and the resistor network for switching the current supplied from the constant current circuit to the resistor network.
    Type: Grant
    Filed: March 23, 1987
    Date of Patent: July 19, 1988
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tetsuya Tateno