Abstract: There is disclosed a method for manufacturing a semiconductor integrated circuit of triple well structure, comprising the steps of forming an N-well, a P-well and a device isolation region in an N-type silicon substrate, thereafter forming a silicon oxide film on the whole surface of the silicon substrate by a thermal oxidation, forming a resist mask covering a region in which the silicon oxide film is required, ion-implanting a P-type impurity using the resist mask as a mask and with an implantation energy enough to allow the ion-implanted impurity to reach a bottom of the N-well and the P-well, so as to form a buried impurity layer, thereafter removing the silicon oxide film not covered with the resist mask by an etching, then removing the resist mask, and conducting a thermal oxidation on the whole surface of the silicon substrate so that a relatively thick gate oxide film is formed on a region which was covered with the resist mask, and a relatively thin gate oxide film is formed on a region which was not

Abstract: There is disclosed a method for manufacturing a semiconductor integrated circuit of triple well structure, comprising the steps of forming an N-well, a P-well and a device isolation region in an N-type silicon substrate, thereafter forming a silicon oxide film on the whole surface of the silicon substrate by a thermal oxidation, forming a resist mask covering a region in which the silicon oxide film is required, ion-implanting a P-type impurity using the resist mask as a mask and with an implantation energy enough to allow the ion-implanted impurity to reach a bottom of the N-well and the P-well, so as to form a buried impurity layer, thereafter removing the silicon oxide film not covered with the resist mask by an etching, then removing the resist mask, and conducting a thermal oxidation on the whole surface of the silicon substrate so that a relatively thick gate oxide film is formed on a region which was covered with the resist mask, and a relatively thin gate oxide film is formed on a region which was not

Abstract: To provide a process for manufacturing a semiconductor integrated circuit device in which ion implantation of an embedded diffused layer for forming triple-well and oxide film etching for forming two types of gate oxide films having different thicknesses is performed by only one photoetching step, the process being capable of reducing the manufacturing cost, and speeding up the circuit operation by making the gate oxide film of the peripheral unit thinner than that of the I/O circuit unit. A resist mask having a given width ranging in a given range which will be formed on the silicon oxide film is formed in a gate forming area in a region where an embedded N-type layer will be formed in a P-type silicon substrate and it is desired to make the thickness of the gate oxide film thicker. The embedded N-type layer is also formed even immediately below the resist mask by conducting an ion implantation at a given energy via the resist mask.

Abstract: In a method of manufacturing a static memory device, a patterning process is performed to a lamination film composed of a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer with regions for load resistors. A lamination section of the first insulating layer and the first conductive layer are separated through the first and second patterning processes into first to fourth portions. The first and second portions respectively functioning as parts of the word line which are connected to each other and as the gates of the transfer MOS transistors, and the third and fourth portions respectively functioning as gates of the drive MOS transistors. The second conductive layer is separated through the second patterning process into fifth and sixth portions, and the fifth and sixth portions respectively functioning as parts of the power supply line which are connected to each other and as the load resistors connected to the parts of the power supply line.

Abstract: A semiconductor static random access memory cell is implemented by four field effect transistors formed on a silicon layer over a buried silicon oxide layer and two resistors formed in an inter-level insulating structure; additional capacitors are formed under the buried silicon oxide layer, and are respectively connected to the gate electrodes of the field effect transistors serving as driving transistors of the memory cell so as to enhance the stability of the memory cell without increase the transistor size.

Abstract: In a virtual ring configuration method and a virtual ring system, a plurality of nodes are set on a plurality of rings and the rings are cross-connected. Each node has a transmitting unit and a receiving unit for sending and receiving service information between the nodes by the SONET path. A judging unit is provided for judging whether or not there is an input of obstruction information by the SONET path. A path protection switch is provided at a receive terminal, which switches the receive terminal which receives the SONET path in cases where the judging unit judges that obstruction information has been received.

Abstract: An optical interface in a SONET system, wherein the optical interface includes a first multiplex/demultiplex apparatus for multiplexing/demultiplexing higher level signals of the main line side and lower level signals of the subscriber side and performing electrical/optical conversion of the lower level electrical signals and optical signals. An optical transmission line is provided for transmitting the optical signals. A second multiplex/demultiplex apparatus converts between the optical signals and a plurality of subscriber side line digital electrical signals. The overhead signals contained in the lower level signals and reaching the first multiplex/demultiplex apparatus are also contained in the optical signals and are transferred further from the first multiplex/demultiplex apparatus to the second multiplex/demultiplex apparatus.

Abstract: A node for a ring type synchronous optical network can continue to communicate with another node, when a transmission path is interrupted, located on the opposite side of the interrupted transmission path. A cross connecting unit cross connects the ring type transmission path with an external transmission path. The cross connecting unit generates and sends to another node an alarm indication signal when the ring type optical path is interrupted. A path switching unit switches the connection of an external transmission path to either direction of the ring type transmission path. A controlling unit controls the path switching unit, when an alarm indication signal is received from another node, so that the path switching unit switches the connection to a side opposite to a side from which the alarm indication signal has been received.

Abstract: A method of predicting the topography of a semiconductor workpiece after a plurality of manufacturing processes, such as etching and film deposition, are carried out on the workpiece includes establishing a desired topography for a semiconductor workpiece after sequential performance of a plurality of processes, such as etching, are carried out on the workpiece; specifying conditions, such as temperature and etchant concentration, for each process; establishing a plurality of points in a grid in a space including the workpiece; identifying the materials comprising the workpiece and the concentration of virtual particles representing the topography of the workpiece before a first process; using the modified diffusion model equation to predict the material and concentration of virtual particles after the completion of the first process in the sequence of processes; recording the material and virtual particle concentration at the completion of the first process as a decimal number including an integer part repre