Abstract: The second-stage nozzles have vanes comprising airfoil profiles substantially in accordance with Cartesian coordinate values of X, Y and Z set forth in inches in Table I with the X, Y and Z values commencing at the radially innermost aerodynamic section of the airfoil and then made relative to that section for the Z coordinate values. The X, Y and Z values may be scaled as a function of the same constant or number to provide a scaled-up or scaled-down airfoil section for the nozzle.

Abstract: The second-stage nozzles have vanes comprising airfoil profiles substantially in accordance with Cartesian coordinate values of X, Y and Z set forth in inches in Table I with the X, Y and Z values commencing at the radially innermost aerodynamic section of the airfoil and then made relative to that section for the Z coordinate values. The X, Y and Z values may be scaled as a function of the same constant or number to provide a scaled-up or scaled-down airfoil section for the nozzle.

Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

Abstract: A test circuit tests for defective memory cells in a memory portion of an Embedded DRAM. The Embedded DRAM includes an array of memory cells. The test circuit includes a test mode terminal adapted to receive a test mode signal and a plurality of comparison circuits. Each comparison circuit includes a first input adapted to receive a read data signal and a second input adapted to receive an expect data signal. Each comparison circuit compares the binary values of the read and expect data signals and develops and inactive error signal on an output when the compared signals have the same binary values, and develops an active error signal when the compared signals have different binary values. A storage circuit is coupled to the outputs of the comparison circuits. The storage circuit latches the error signals output by the comparison circuits and sequentially transfers the latched error signals onto a data terminal of the Embedded DRAM.

Abstract: The third-stage nozzles have vanes comprising airfoil profiles substantially in accordance with Cartesian coordinate values of X, Y and Z set forth in inches in Table I wherein Z is a perpendicular distance from a plane normal to a radius of the turbine centerline and containing the X and Y values with the Z value commencing at zero in the X, Y plane at the radially innermost aerodynamic section of the airfoil and X and Y are coordinate values defining the airfoil profile at each distance Z. The X, Y and Z values may be scaled as a function of the same constant or number to provide a scaled-up or scaled-down airfoil section for each nozzle vane.

Abstract: A semiconductor memory device and a method of making and using a semiconductor memory device containing a word line design, which is used in ultra-large scale integrated (ULSI) circuits, that produces a device with a lower RC time constant than devices formed using prior art techniques. In one embodiment of the invention low resistivity metal strapping layers are attached to alternating halves of wordlines in a single memory array. The alternating pattern allows the low resistivity of the strapping layers to be utilized without introducing significant negative capacitive resistance effects due to strapping layers being too close to each other.

Abstract: A memory device having a plurality of programming circuits. The programming circuits connect to an input pad to receive a programming voltage. When one of the programming circuits is activated during a programming operation, the activated programming circuit passes the programming voltage to a programming node connected to it. Non-activated programming circuits only pass a portion of the programming voltage to other programming nodes connected to them.

Abstract: A circuit and method for selectively coupling redundant components into an integrated circuit. Global I/O lines are coupled to local I/O lines through a number of multiplexors. Bitlines are grouped into blocks of bitlines. A fuse bank couples to the number of multiplexors through a logic/select circuit. When at least one fuse's state indicates that the associated I/O line is inoperable, the logic/select circuit switches the coupling to connect the global I/O line with a redundant local I/O line. The redundant local I/O's are configured to access the original block of bitlines. The arrangement conserves precious chip space and preserves uniform timing between normal and redundant data.

Abstract: A buffer circuit (10). The buffer circuit (10) includes a first inverter (12) with a first current limiter (18) that limits the standby current used by the first inverter (12). Further, the buffer circuit (10) includes a second inverter (14) that is coupled to an output of the first inverter (12). The input buffer (10) converts a first logic level of an input signal provided to the first inverter (12) to a second logic level at an output of the second inverter (14). The buffer circuit (10) also includes a second current limiting circuit (16) that is coupled between the first and second inverters (12 and 14) to further limit the standby current in the buffer circuit (10).

Abstract: A circuit and method for selectively coupling redundant components into an integrated circuit. Global I/O lines are coupled to local I/O lines through a number of multiplexors. Bitlines are grouped into blocks of bitlines. A fuse bank couples to the number of multiplexors through a logic/select circuit. When at least one fuse's state indicates that the associated I/O line is inoperable, the logic/select circuit switches the coupling to connect the global I/O line with a redundant local I/O line. The redundant local I/O's are configured to access the original block of bitlines. The arrangement conserves precious chip space and preserves uniform timing between normal and redundant data.

Abstract: A test circuit tests for defective memory cells in a memory portion of an Embedded DRAM. The Embedded DRAM includes an array of memory cells. The test circuit includes a test mode terminal adapted to receive a test mode signal and a plurality of comparison circuits. Each comparison circuit includes a first input adapted to receive a read data signal and a second input adapted to receive an expect data signal. Each comparison circuit compares the binary values of the read and expect data signals and develops and inactive error signal on an output when the compared signals have the same binary values, and develops an active error signal when the compared signals have different binary values. A storage circuit is coupled to the outputs of the comparison circuits. The storage circuit latches the error signals output by the comparison circuits and sequentially transfers the latched error signals onto a data terminal of the Embedded DRAM.

Abstract: A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle.

Abstract: A buffer circuit (10). The buffer circuit (10) includes a first inverter (12) with a first current limiter (18) that limits the standby current used by the first inverter (12). Further, the buffer circuit (10) includes a second inverter (14) that is coupled to an output of the first inverter (12). The input buffer (10) converts a first logic level of an input signal provided to the first inverter (12) to a second logic level at an output of the second inverter (14). The buffer circuit (10) also includes a second current limiting circuit (16) that is coupled between the first and second inverters (12 and 14) to further limit the standby current in the buffer circuit (10).

Abstract: A buffer circuit (10). The buffer circuit (10) includes a first inverter (12) with a first current limiter (18) that limits the standby current used by the first inverter (12). Further, the buffer circuit (10) includes a second inverter (14) that is coupled to an output of the first inverter (12). The input buffer (10) converts a first logic level of an input signal provided to the first inverter (12) to a second logic level at an output of the second inverter (14). The buffer circuit (10) also includes a second current limiting circuit (16) that is coupled between the first and second inverters (12 and 14) to further limit the standby current in the buffer circuit (10).

Abstract: A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle.

Abstract: A programmable multiconfiguration data port clocking system for use in asynchronous transfer mode communication (ATM) networks. The clocking system is programmed using a number of preselected configuration codes to automatically switch the clocking of the data port configuration of an ATM network chip. The clocking system incorporates an automatic disable circuit for eliminating random outputs from unused pins in the clocking hardware. The clocking system also employs a noise suppression circuit for reducing spurious noise into the ATM network.

Abstract: An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.

Abstract: A multiport interface for digital communication systems having pipelined multiplexing of port instructions for increased throughput. The multiport interface includes an analog delay for independent timing of asynchronous operations, such as memory accesses. The multiport interface also has an instruction pipeline and multiplexer to coordinate a number of port instructions.

Abstract: An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.