Patents by Inventor Theo Alan Drane
Theo Alan Drane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10606558Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.Type: GrantFiled: April 18, 2019Date of Patent: March 31, 2020Assignee: Imagination Technologies LimitedInventor: Theo Alan Drane
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Publication number: 20200089471Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Inventors: Theo Alan Drane, Wai-Chuen Cheung
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Patent number: 10540141Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.Type: GrantFiled: December 21, 2018Date of Patent: January 21, 2020Assignee: Imagination Technologies LimitedInventors: Theo Alan Drane, Wai-Chuen Cheung
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Publication number: 20190286422Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.Type: ApplicationFiled: June 3, 2019Publication date: September 19, 2019Inventors: Freddie Rupert Exall, Theo Alan Drane, Joe Buckingham
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Publication number: 20190243608Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Inventor: Theo Alan Drane
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Patent number: 10346137Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.Type: GrantFiled: October 4, 2018Date of Patent: July 9, 2019Assignee: Imagination Technologies LimitedInventors: Freddie Rupert Exall, Theo Alan Drane, Joe Buckingham
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Patent number: 10331405Abstract: An accurate implementation of a polynomial using floating-point or other rounded arithmetic can be generated using a plurality of hardware logic components which each implement an input polynomial such that the zeros in the input polynomial can be determined correctly. The number of different hardware logic components that are used can be reduced by analyzing the set of input polynomials and from it generating a set of polynomial components, where each polynomial in the set of input polynomials which is not also in the set of polynomial components, can be generated from a single one of the polynomial components.Type: GrantFiled: April 21, 2017Date of Patent: June 25, 2019Assignee: Imagination Technologies LimitedInventor: Theo Alan Drane
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Publication number: 20190187956Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.Type: ApplicationFiled: December 21, 2018Publication date: June 20, 2019Inventors: Theo Alan Drane, Wai-Chuen Cheung
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Publication number: 20190171415Abstract: Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.Type: ApplicationFiled: January 18, 2019Publication date: June 6, 2019Inventor: Theo Alan Drane
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Patent number: 10310816Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.Type: GrantFiled: June 27, 2017Date of Patent: June 4, 2019Assignee: Imagination Technologies LimitedInventor: Theo Alan Drane
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Patent number: 10296293Abstract: Methods of implementing fixed-point polynomials in hardware logic include distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial by solving an optimization problem that outputs an accuracy parameter and a precision parameter for each node. Each operator is then itself optimized to satisfy the part of the error bound allocated to that operator and as defined by the accuracy and precision parameters.Type: GrantFiled: June 27, 2017Date of Patent: May 21, 2019Assignee: Imagination Technologies LimitedInventor: Theo Alan Drane
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Patent number: 10223068Abstract: Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.Type: GrantFiled: June 28, 2017Date of Patent: March 5, 2019Assignee: Imagination Technologies LimitedInventor: Theo Alan Drane
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Publication number: 20190034171Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.Type: ApplicationFiled: October 4, 2018Publication date: January 31, 2019Inventors: Freddie Rupert Exall, Theo Alan Drane, Joe Buckingham
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Patent number: 10185545Abstract: A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also comprise one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.Type: GrantFiled: July 6, 2018Date of Patent: January 22, 2019Assignee: Imagination Technologies LimitedInventors: Freddie Rupert Exall, Theo Alan Drane
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Patent number: 10175943Abstract: An efficient hardware apparatus for calculating the maximum and/or minimum of two n-bit binary input values generates a number of separate select signals, each of which is then used to control the selection of a single bit from one of the two binary inputs. A select signal for an ith bit of the output depends upon bits [n?1, i] in each of the two binary inputs and based on the select signal the ith bit is selected from one of the two inputs.Type: GrantFiled: April 26, 2017Date of Patent: January 8, 2019Assignee: Imagination Technologies LimitedInventors: Theo Alan Drane, Thomas Michael Rose
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Patent number: 10162600Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.Type: GrantFiled: February 17, 2018Date of Patent: December 25, 2018Assignee: Imagination Technologies LimitedInventors: Theo Alan Drane, Wai-Chuen Cheung
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Patent number: 10120651Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.Type: GrantFiled: September 12, 2016Date of Patent: November 6, 2018Assignee: Imagination Technologies LimitedInventors: Freddie Rupert Exall, Theo Alan Drane, Joe Buckingham
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Publication number: 20180314494Abstract: A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also comprise one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.Type: ApplicationFiled: July 6, 2018Publication date: November 1, 2018Inventors: Freddie Rupert Exall, Theo Alan Drane
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Publication number: 20180239585Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.Type: ApplicationFiled: February 17, 2018Publication date: August 23, 2018Inventors: Theo Alan Drane, Wai-Chuen Cheung
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Patent number: 10042610Abstract: A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also comprise one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.Type: GrantFiled: November 12, 2017Date of Patent: August 7, 2018Assignee: Imagination Technolgies LimitedInventors: Freddie Rupert Exall, Theo Alan Drane