Abstract: A method is provided for deriving an RTL a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position. In this, an error requirement to meet for the design rounding position is derived. For each of the CCT and the VCT implementation a number columns to discard is derived and a constant to include in the sum addends. For an LMS implementation, a number of columns to discard is derived. After discarding the columns and including the constants as appropriate, an RTL representation of the sum of addends operation is derived for each of the CCT, VCT and LMS implementations and a logic circuit synthesized for each of these. The logic circuit which gives the best implementation is selected for manufacture.

Abstract: A method is provided for a synthesising In RTL, a logic circuit and for manufacturing an integrated circuit for performing a sum of addends with faithful rounding. In this, optimisation constraints for a value of bits which may be discarded and a constant to include in a sum of addends are determined (20). Next, the maximum number of whole columns that can be removed from the sum of addends array is derived (22) and those columns are discarded (24). Next, a number of bits which can be removed from the least significant column is derived (26) and these bits are discarded (28). The constant is included in the sum of addends and a logic array synthesised in RTL (31) before manufacturing an integrated circuit.

Abstract: A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the data flow graph representations are restricted (52) to provide a first modified version of each of the designs. These first modified versions are compared each with the design from which it was derived in a comparison unit (54). The input bit widths of the data flow graph representation are then restricted to be no wider than the output bit widths (56) to derive second modified versions of the designs (58). These second modified versions are compared with each other (60) to determine which are equivalent. Equivalent designs can be passed to an RTL synthesis unit 62, or otherwise further evaluated.

Abstract: A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the data flow graph representations are restricted (52) to provide a first modified version of each of the designs. These first modified versions are compared each with the design from which it was derived in a comparison unit (54). The input bit widths of the data flow graph representation are then restricted to be no wider than the output bit widths (56) to derive second modified versions of the designs (58). These second modified versions are compared with each other (60) to determine which are equivalent. Equivalent designs can be passed to an RTL synthesis unit 62, or otherwise further evaluated.

Abstract: A hardware circuit component for executing multiple sum-of-products operations is manufactured as follows. A set of multiplexed sum-of-products functions of a plurality of operands (a, b, c, . . . ), any one of which functions can be selected in dependence upon a select value (sel) by multiplex operations, is received. The sum-of-products functions are then rearranged in a particular manner. The rearranged set of sum-of-products functions is merged into a single merged sum-of-products function containing one or more multiplexing operations. From this a layout design can be generated, and a hardware circuit component such as an integrated circuit manufactured from the layout design. The step of re-arranging the multiple sum-of-products functions involves aligning the elements of the set of sum-of-products functions in such a manner that the amount of multiplexing in the single merged sum-of-products function is less than in the input set of sum-of-products functions.

Abstract: A method is provided for deriving an RTL a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position. In this, an error requirement to meet for the design rounding position is derived. For each of the CCT and the VCT implementation a number columns to discard is derived and a constant to include in the sum addends. For an LMS implementation, a number of columns to discard is derived. After discarding the columns and including the constants as appropriate, an RTL representation of the sum of addends operation is derived for each of the CCT, VCT and LMS implementations and a logic circuit synthesized for each of these. The logic circuit which gives the best implementation is selected for manufacture.

Abstract: A hardware circuit component for executing multiple sum-of-products operations is manufactured as follows. A set of multiplexed sum-of-products functions of a plurality of operands (a, b, c, . . . ), any one of which functions can be selected in dependence upon a select value (sel) by multiplex operations, is received. The sum-of-products functions are then rearranged in a particular manner. The rearranged set of sum-of-products functions is merged into a single merged sum-of-products function containing one or more multiplexing operations. From this a layout design can be generated, and a hardware circuit component such as an integrated circuit manufactured from the layout design. The step of re-arranging the multiple sum-of-products functions comprises aligning the elements of the set of sum-of-products functions in such a manner that the amount of multiplexing in the single merged sum-of-products function is less than in the input set of sum-of-products functions.