Abstract: Nanowire fluid sensors are provided. The fluid sensors comprise a first electrode, a second electrode, and at least one nanowire between the first electrode and the second electrode. Each nanowire is connected at a first end to the first electrode and at a second end to the second electrode. Methods of fabricating and operating the fluid sensor are also provided.

Abstract: A semiconductor nanowire is grown laterally. A method of growing the nanowire forms a vertical surface on a substrate, and activates the vertical surface with a nanoparticle catalyst. A method of laterally bridging the nanowire grows the nanowire from the activated vertical surface to connect to an opposite vertical surface on the substrate. A method of connecting electrodes of a semiconductor device grows the nanowire from an activated device electrode to an opposing device electrode. A method of bridging semiconductor nanowires grows nanowires between an electrode pair in opposing lateral directions. A method of self-assembling the nanowire bridges the nanowire between an activated electrode pair. A method of controlling nanowire growth forms a surface irregularity in the vertical surface. An electronic device includes a laterally grown nano-scale interconnection.

Abstract: A method is provided for forming smooth polycrystalline silicon electrodes for molecular electronic devices. The method comprises: depositing a silicon layer in an amorphous form; forming a native oxide on a surface of the amorphous silicon layer at a temperature between room temperature to 500° C.; and converting the amorphous silicon to polycrystalline silicon by heat-treating at a temperature in a range of 600° to 800° C. for a period of time in a range of 1 minute to 24 hrs, with higher temperatures associated with shorter times, in an inert atmosphere. The method converts the amorphous form of silicon to the higher conductivity polycrystalline form, while retaining the smoothness associated with the amorphous form.

Abstract: An optical modulator includes a confinement region of semiconductor material defining at least a portion of a light path through the optical modulator. The optical modulator also includes electrical contacts for connection with a voltage source for injecting carriers into the confinement region. The injected carriers impede light propagating through the confinement region, to thereby modulate light intensity. Contact regions in electrical contact with the confinement region remove injected carriers from the confinement region. Methods of modulating light and of making the optical modulator are also disclosed.

Abstract: A nanowire includes a single crystalline semiconductor material having an exterior surface and an interior region and at least one dopant atom. At least a portion of the nanowire thermally switches between two conductance states; a high conductance state, where a high fraction of the dopant atoms is in the interior region, and a low conductance state, where a lower fraction of the dopant atoms is at the interior region and a higher fraction of the atoms is at the exterior surface.

Abstract: A field effect transistor having a narrow channel and a method for forming such a device. An upstanding nanopillar is formed from a substrate by directional etching of the substrate preferentially masked by a nanoparticle. A stack of planar layers of material is formed adjacent and around the nanopillar. The bottom layer, adjacent the substantially planar top substrate surface, comprises insulating material. A conductive gate layer overlies the bottom layer while a second insulating layer overlies the gate layer. The pillar material is etched to leave a nanopore into which semiconductor material is deposited, forming an upstanding channel, after insulating material has been deposited on the interior of the nanopore. The source or drain may be a conductive substrate or a doped region of the substrate formed immediately beneath the nanopillar with the other electrode formed by doping the region adjacent the top of the channel.

Abstract: A method is provided for forming smooth polycrystalline silicon electrodes for molecular electronic devices. The method comprises: depositing a silicon layer in an amorphous form; forming a native oxide on a surface of the amorphous silicon layer at a temperature between room temperature to 500° C.; and converting the amorphous silicon to polycrystalline silicon by heat-treating at a temperature in a range of 600° to 800° C. for a period of time in a range of 1 minute to 24 hrs, with higher temperatures associated with shorter times, in an inert atmosphere. The method converts the amorphous form of silicon to the higher conductivity polycrystalline form, while retaining the smoothness associated with the amorphous form.

Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.

Abstract: A field effect transistor (FET) has a channel formed in a pore extending up from a conductive portion of a substrate through a stack of planar layers including a first insulating layer, a gate layer, and a second insulating layer. The pore can be upright or inclined relative to the layers. A nanoparticle used for a mask of a directional etching process ultimately defines the size of the pore and therefore the channel width. The substrate or a doped region of the substrate formed immediately beneath the channel can be a source/drain of the FET with the other drain/source being a doped region adjacent the top of the channel. The gate layer can form the gate or can contact a separate gate inside the pore.

Abstract: A field effect transistor having a narrow channel and a method for forming such a device. An upstanding nanopillar is formed from a substrate by directional etching of the substrate preferentially masked by a nanoparticle. A stack of planar layers of material is formed adjacent and around the nanopillar. The bottom layer, adjacent the substantially planar top substrate surface, comprises insulating material. A conductive gate layer overlies the bottom layer while a second insulating layer overlies the gate layer. The pillar material is etched to leave a nanopore into which semiconductor material is deposited, forming an upstanding channel, after insulating material has been deposited on the interior of the nanopore. The source or drain may be a conductive substrate or a doped region of the substrate formed immediately beneath the nanopillar with the other electrode formed by doping the region adjacent the top of the channel.

Abstract: A gated nanoscale switch operates as a resonant tunneling device. A conductive channel is formed of a pair of conductive molecular wires and a conductive nanoparticle. Each molecular wire is bound, at one end, to the conductive nanoparticle and, at the opposed end, to one of a pair of electrodes. The structure is located upon a dielectric layer that overlies a conductive substrate. The device may be arranged to operate as a switch with the conductive substrate acting as a gate electrode. Alternatively, the device may be employed to measure the electrical (current versus voltage) characteristics of the molecular wires.

Abstract: Self-organized, or self-assembled, nanowires of a first composition may be used as an etching mask for fabrication of nanowires of a second composition. The method for forming such nanowires comprises: (a) providing an etchable layer of the second composition and having a buried insulating layer beneath a major surface thereof; (b) growing self-assembled nanowires on the surface of the etchable layer; and (c) etching the etchable layer anisotropically down to the insulating layer, using the self-assembled nanowires as a mask. The self-assembled nanowires may be removed or left. In either event, nanowires of the second composition are formed. The method enables the formation of one-dimensional crystalline nanowires with widths and heights at the nanometer scale, and lengths at the micrometer scale, which are aligned along certain crystallographic directions with high crystal quality.

Abstract: A field effect transistor having a narrow channel and a method for forming such a device. An upstanding nanopillar is formed from a substrate by directional etching of the substrate preferentially masked by a nanoparticle. A stack of planar layers of material is formed adjacent and around the nanopillar. The bottom layer, adjacent the substantially planar top substrate surface, comprises insulating material. A conductive gate layer overlies the bottom layer while a second insulating layer overlies the gate layer. The pillar material is etched to leave a nanopore into which semiconductor material is deposited, forming an upstanding channel, after insulating material has been deposited on the interior of the nanopore. The source or drain may be a conductive substrate or a doped region of the substrate formed immediately beneath the nanopillar with the other electrode formed by doping the region adjacent the top of the channel.

Abstract: Methods for forming a predetermined pattern of catalytic regions having nanoscale dimensions are provided for use in the growth of nanowires. The methods include one or more nanoimprinting steps to produce arrays of catalytic nanoislands or nanoscale regions of catalytic material circumscribed by noncatalytic material.

Abstract: A method of forming an assembly of isolated nanowires of at least one material within a matrix of another material is provided. The method comprises: providing a substrate; forming a catalyst array on a major surface of the substrate; growing an array of the nanowires corresponding with the catalyst array, the nanowires, each comprising at least one material; and forming a matrix of another material that fills in spaces between the nanowires. The method is useful for producing a variety of structures useful in a number of devices, such as photonic bandgap structures and quantum dot structures.

Abstract: A method of fabricating nanosized holes with controlled geometries employs tools and methods developed in the microelectronics industry. The method exploits the fact that epitaxially grown film thicknesses can be controlled within a few atomic monolayers and that by using etching techniques, trenches and channels can be created that are only a few nanometers wide. The method involves bonding two shallow channels at an angle such that a nanopore is defined by the intersection. Thus, a nanopore-defining device includes a nanopore with dimensions that are determined by the dimensions and orientations of the intersecting channels, with the dimensions being accurately controlled within a few monolayers.

Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.

Abstract: A method is provided for forming smooth polycrystalline silicon electrodes for molecular electronic devices. The method comprises: depositing a silicon layer in an amorphous form; forming a native oxide on a surface of the amorphous silicon layer at a temperature between room temperature to 500° C.; and converting the amorphous silicon to polycrystalline silicon by heat-treating at a temperature in a range of 600° to 800° C. for a period of time in a range of 1 minute to 24 hrs, with higher temperatures associated with shorter times, in an inert atmosphere. The method converts the amorphous form of silicon to the higher conductivity polycrystalline form, while retaining the smoothness associated with the amorphous form.

Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.

Abstract: A technique is provided for forming a molecule or an array of molecules having a defined orientation relative to the substrate or for forming a mold for deposition of a material therein. The array of molecules is formed by dispersing them in an array of small, aligned holes (nanopores), or mold, in a substrate. Typically, the material in which the nanopores are formed is insulating. The underlying substrate may be either conducting or insulating. For electronic device applications, the substrate is, in general, electrically conducting and may be exposed at the bottom of the pores so that one end of the molecule in the nanopore makes electrical contact to the substrate. A substrate such as a single-crystal silicon wafer is especially convenient because many of the process steps to form the molecular array can use techniques well developed for semiconductor device and integrated-circuit fabrication.