Patents by Inventor Theodore Kamins

Theodore Kamins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9123705
    Abstract: Vias (holes) are formed in a wafer or a dielectric layer. A low viscosity conductive ink, containing microscopic metal particles, is deposited over the top surface of the wafer to cover the vias. An external force is applied to urge the ink into the vias, including an electrical force, a magnetic force, a centrifugal force, a vacuum, or a suction force for outgassing the air in the vias. Any remaining ink on the surface is removed by a squeegee, spinning, an air knife, or removal of an underlying photoresist layer. The ink in the vias is heated to evaporate the liquid and sinter the remaining metal particles to form a conductive path in the vias. The resulting wafer may be bonded to one or more other wafers and singulated to form a 3-D module.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: September 1, 2015
    Assignee: Nthdegree Technologies Worldwide Inc.
    Inventors: Richard A. Blanchard, William J. Ray, Mark D. Lowenthal, Xiaorong Cai, Theodore Kamins
  • Publication number: 20150076711
    Abstract: Vias (holes) are formed in a wafer or a dielectric layer. A low viscosity conductive ink, containing microscopic metal particles, is deposited over the top surface of the wafer to cover the vias. An external force is applied to urge the ink into the vias, including an electrical force, a magnetic force, a centrifugal force, a vacuum, or a suction force for outgas sing the air in the vias. Any remaining ink on the surface is removed by a squeegee, spinning, an air knife, or removal of an underlying photoresist layer. The ink in the vias is heated to evaporate the liquid and sinter the remaining metal particles to form a conductive path in the vias. The resulting wafer may be bonded to one or more other wafers and singulated to form a 3-D module.
    Type: Application
    Filed: November 24, 2014
    Publication date: March 19, 2015
    Inventors: Richard A. Blanchard, William J. Ray, Mark D. Lowenthal, Xiaorong Cai, Theodore Kamins
  • Patent number: 8940627
    Abstract: Vias (holes) are formed in a wafer or a dielectric layer. A low viscosity conductive ink, containing microscopic metal particles, is deposited over the top surface of the wafer to cover the vias. An external force is applied to urge the ink into the vias, including an electrical force, a magnetic force, a centrifugal force, a vacuum, or a suction force for outgassing the air in the vias. Any remaining ink on the surface is removed by a squeegee, spinning, an air knife, or removal of an underlying photoresist layer. The ink in the vias is heated to evaporate the liquid and sinter the remaining metal particles to form a conductive path in the vias. The resulting wafer may be bonded to one or more other wafers and singulated to form a 3-D module.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: January 27, 2015
    Assignee: Nthdegree Technologies Worldwide Inc.
    Inventors: Richard A. Blanchard, William J. Ray, Mark D. Lowenthal, Xiaorong Cai, Theodore Kamins
  • Publication number: 20110181318
    Abstract: An electrically, thermally, or electrically and thermally actuated device is disclosed herein. The device includes a substrate, a first electrode established on the substrate, an active region established on the electrode, and a second electrode established on the active region. A pattern is defined in at least one of the substrate, the first electrode, the second electrode, or the active region. At least one of grain boundaries are formed within, or surface asperities are formed on, at least one of the electrodes or the active region. The pattern controls the at least one of the grain boundaries or surface asperities.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 28, 2011
    Inventor: Theodore Kamins
  • Publication number: 20070284734
    Abstract: An embodiment of an integrated circuit comprises active components in more than one active layer. A first conductor in one active layer is operative to produce a static electric field that controls a first active element in an adjacent active layer.
    Type: Application
    Filed: May 22, 2006
    Publication date: December 13, 2007
    Inventors: Theodore Kamins, Philip Kuekes
  • Publication number: 20070252132
    Abstract: A radiation-emitting device includes a nanowire that is structurally and electrically coupled to a first electrode and a second electrode. The nanowire includes a double-heterostructure semiconductor device configured to emit electromagnetic radiation when a voltage is applied between the electrodes. A device includes a nanowire having an active longitudinal segment selectively disposed at a predetermined location within a resonant cavity that is configured to resonate at least one wavelength of electromagnetic radiation emitted by the segment within a range extending from about 300 nanometers to about 2,000 nanometers. Active nanoparticles are precisely positioned in resonant cavities by growing segments of nanowires at known growth rates for selected amounts of time.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Inventors: Theodore Kamins, Philip Kuekes, Stanley Williams
  • Publication number: 20070252979
    Abstract: A nano-enhanced Raman scattering (NERS)-active structure includes a substrate, a monolayer of nanoparticles disposed on a surface of the substrate, and a spacer material surrounding each nanoparticle in the monolayer of nanoparticles. The monolayer of nanoparticles includes a first plurality of nanoparticles and a second plurality of nanoparticles. The nanoparticles of the second plurality are interspersed among the first plurality and exhibit a plasmon frequency that differs from any plasmon frequency exhibited by the first plurality. Also described are a method for forming such a NERS-active structure and a NERS system that includes a NERS-active structure, an excitation radiation source, and a detector for detecting Raman scattered radiation.
    Type: Application
    Filed: March 25, 2005
    Publication date: November 1, 2007
    Inventors: Alexandre Bratkovski, Theodore Kamins
  • Publication number: 20070254169
    Abstract: Structures including a substrate having a nano-patterned surface, and a self-assembled monolayer of an organic material on the nano-patterned surface are provided. The self-assembled monolayer is ordered with respect to features of the nano-patterned surface. Methods of making the structures and filament switching devices including a self-assembled monolayer are also provided.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Inventors: Theodore Kamins, Douglas Ohlberg, Amir Yasseri
  • Publication number: 20070252982
    Abstract: Raman systems include a radiation source, a radiation detector, and a Raman device or signal-enhancing structure. Raman devices include a tunable resonant cavity and a Raman signal-enhancing structure coupled to the cavity. The cavity includes a first reflective member, a second reflective member, and an electro-optic material disposed between the reflective members. The electro-optic material exhibits a refractive index that varies in response to an applied electrical field. Raman signal-enhancing structures include a substantially planar layer of Raman signal-enhancing material having a major surface, a support structure extending from the major surface, and a substantially planar member comprising a Raman signal-enhancing material disposed on an end of the support structure opposite the layer of Raman signal-enhancing material. The support structure separates at least a portion of the planar member from the layer of Raman signal-enhancing material by a selected distance of less than about fifty nanometers.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Inventors: Shih-Yuan Wang, R. Williams, Raymond Beausoleil, Theodore Kamins, Zhiyong Li, Wei Wu
  • Publication number: 20070228459
    Abstract: An integrated semiconductor circuit includes a substrate having a surface of a first semiconductor material, at least one separating material formed on the surface and defining a through hole, and a guide region formed in the hole. The guide region comprises at least one second semiconductor material. The guide region comprises at least a first region and a second region having a larger cross-section than the first region. The first region contacts the surface of the substrate over a small contact region. Methods of making the integrated semiconductor circuit are also disclosed.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventor: Theodore Kamins
  • Publication number: 20070228583
    Abstract: A semiconductor nanowire is grown laterally. A method of growing the nanowire forms a vertical surface on a substrate, and activates the vertical surface with a nanoparticle catalyst. A method of laterally bridging the nanowire grows the nanowire from the activated vertical surface to connect to an opposite vertical surface on the substrate. A method of connecting electrodes of a semiconductor device grows the nanowire from an activated device electrode to an opposing device electrode. A method of bridging semiconductor nanowires grows nanowires between an electrode pair in opposing lateral directions. A method of self-assembling the nanowire bridges the nanowire between an activated electrode pair. A method of controlling nanowire growth forms a surface irregularity in the vertical surface. An electronic device includes a laterally grown nano-scale interconnection.
    Type: Application
    Filed: February 23, 2007
    Publication date: October 4, 2007
    Inventors: M. Islam, Theodore Kamins, Shashank Sharma
  • Publication number: 20070177139
    Abstract: A NERS-active structure is disclosed that includes at least one heterostructure nanowire. The at least one heterostructure nanowire may include alternating segments of an NERS-inactive material and a NERS-active material in an axial direction. Alternatively, the alternating segments may be of an NERS-inactive material and a material capable of attracting nanoparticles of a NERS-active material. In yet another alternative, the heterostructure nanowire may include a core with alternating coatings of an NERS-inactive material and a NERS-active material in a radial direction. A NERS system is also disclosed that includes a NERS-active structure. Also disclosed are methods for forming a NERS-active structure and methods for performing NERS with NERS-active structures.
    Type: Application
    Filed: January 27, 2006
    Publication date: August 2, 2007
    Inventors: Theodore Kamins, Alexandre Bratkovski, Shashank Sharma
  • Publication number: 20070178709
    Abstract: The growth of nanowires with a narrow diameter distribution is provided. The growth comprises: providing a substrate; providing a plurality of nanoparticles having a distribution of particle sizes on the substrate; initiating growth of nanowires by a vapor-liquid-solid technique; and terminating growth of the nanowires.
    Type: Application
    Filed: June 21, 2005
    Publication date: August 2, 2007
    Inventor: Theodore Kamins
  • Publication number: 20070105356
    Abstract: Nanowire growth in situ on a planar surface, which is one of a crystalline surface having any crystal orientation, a polycrystalline surface and a non-crystalline surface, is controlled by guiding catalyzed growth of the nanowire from the planar surface in a nano-throughhole of a patterned layer formed on the planar surface, such that the nanowire grows in situ perpendicular to the planar surface. An electronic device includes first and second regions of electronic circuitry vertically spaced by the patterned layer. The nano-throughhole of the patterned layer extends perpendicularly between the regions. The first region has the planar surface. The device further includes a nanowire extending perpendicular from a catalyst location on the planar surface of the first region in the nano-throughhole. The nanowire forms a component of a nano-scale circuit that connects the regions.
    Type: Application
    Filed: November 10, 2005
    Publication date: May 10, 2007
    Inventors: Wei Wu, Theodore Kamins, Shashank Sharma, R. Williams
  • Publication number: 20070096231
    Abstract: An apparatus comprising an integrated circuit having a plurality of devices each having device characteristics, and a waveguide structure coupled to the integrated circuit, wherein photons provided to the waveguide structure are directed to one or more devices of the plurality of devices and can alter the device characteristics of the device or devices.
    Type: Application
    Filed: November 1, 2005
    Publication date: May 3, 2007
    Inventors: Philip Kuekes, Theodore Kamins
  • Publication number: 20060209300
    Abstract: Methods of forming NERS-active structures are disclosed that include ordered arrays of nanoparticles. Nanoparticles covered with an outer shell may be arranged in an ordered array on a substrate using Langmuir-Blodgett techniques. A portion of the outer shell may be removed, and the exposed nanoparticles may be used in a system to perform nanoenhanced Raman spectroscopy. An ordered array of nanoparticles may be used as a mask for forming islands of NERS-active material on a substrate. NERS-active structures and an NERS system that includes an NERS-active structure are also disclosed. Also disclosed are methods for performing NERS with NERS-active structures.
    Type: Application
    Filed: March 17, 2005
    Publication date: September 21, 2006
    Inventors: Theodore Kamins, Alexandre Bratkovski, Shashank Sharma
  • Publication number: 20060164634
    Abstract: An NERS-active structure is disclosed that includes a substrate and at least one elongated component disposed on the substrate. The at least one elongated component may include two conducting strips including an NERS-active material and an insulating strip positioned between the two conducting strips. Alternatively, the at least one elongated component may include a homogeneous component. An NERS system is also disclosed that includes an NERS-active structure. Also disclosed are methods for forming an NERS-active structure and methods for performing NERS with NERS-active structures.
    Type: Application
    Filed: January 27, 2005
    Publication date: July 27, 2006
    Inventors: Theodore Kamins, R. Stanley Williams
  • Publication number: 20060146323
    Abstract: A SERS-active structure is disclosed that includes a substrate and at least two nanowires disposed on the substrate. Each of the at least two nanowires has a first end and a second end, the first end being attached to the substrate and the second end having a SERS-active tip. A SERS system is also disclosed that includes a SERS-active structure. Also disclosed are methods for forming a SERS-active structure and methods for performing SERS with SERS-active structures.
    Type: Application
    Filed: January 6, 2005
    Publication date: July 6, 2006
    Inventors: Alexandre Bratkovski, M. Islam, Theodore Kamins, Zhiyong Li, Shih-Yuan Wang
  • Publication number: 20060138575
    Abstract: Nanowire fluid sensors are provided. The fluid sensors comprise a first electrode, a second electrode, and at least one nanowire between the first electrode and the second electrode. Each nanowire is connected at a first end to the first electrode and at a second end to the second electrode. Methods of fabricating and operating the fluid sensor are also provided.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 29, 2006
    Inventor: Theodore Kamins
  • Publication number: 20050200020
    Abstract: A method is provided for forming smooth polycrystalline silicon electrodes for molecular electronic devices. The method comprises: depositing a silicon layer in an amorphous form; forming a native oxide on a surface of the amorphous silicon layer at a temperature between room temperature to 500° C.; and converting the amorphous silicon to polycrystalline silicon by heat-treating at a temperature in a range of 600° to 800° C. for a period of time in a range of 1 minute to 24 hrs, with higher temperatures associated with shorter times, in an inert atmosphere. The method converts the amorphous form of silicon to the higher conductivity polycrystalline form, while retaining the smoothness associated with the amorphous form.
    Type: Application
    Filed: May 11, 2005
    Publication date: September 15, 2005
    Inventor: Theodore Kamins