Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A complementary metal-oxide-semiconductor field-effect transistor (CMOS) device includes a first source/drain (S/D) region and a second S/D region different from the first S/D region. A first epitaxy film formed of a first semiconductor material is on the first S/D region. A second epitaxy film formed of a second semiconductor material is on the second S/D region. The CMOS device further includes first and second S/D contact stacks. The first S/D contact stack includes a first contact trench liner having a first inner side wall extending from a first base portion to an upper surface of the first S/D contact stack. The second S/D contact stack includes a second contact trench liner having a second inner side wall extending from a second base portion to an upper surface of the second S/D contact stack. The first inner sidewall directly contacts the second inner sidewall.

Abstract: A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes a screen layer over tops of the fins. An etch stop feature is formed on the screen layer. The etch stop feature is patterned down to the screen layer in regions across the device. A dummy gate material formed over the fins is planarized down to the etch stop feature, a dielectric fill between gate structures patterned from the dummy gate material is planarized down to the etch stop feature and a gate conductor is planarized to the etch stop feature.

Abstract: A method of forming a resistor adjacent to a fin field effect transistor on a substrate, including, forming a plurality of vertical fins on the substrate, forming a dielectric fill layer on the plurality of vertical fins, forming at least two dummy gate structures on the plurality of vertical fins, forming a replaceable resistor structure on the dielectric fill layer over a region of the substrate unoccupied by vertical fins, forming a sidewall spacer on the at least two dummy gate structures and the replaceable resistor structure, removing the replaceable resistor structure to form a trench, and forming a resistor structure in the trench.

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

Abstract: A complementary metal-oxide-semiconductor field-effect transistor (CMOS) device includes a first source/drain (S/D) region and a second S/D region different from the first S/D region. A first epitaxy film formed of a first semiconductor material is on the first S/D region. A second epitaxy film formed of a second semiconductor material is on the second S/D region. The CMOS device further includes first and second S/D contact stacks. The first S/D contact stack includes a first contact trench liner having a first inner side wall extending from a first base portion to an upper surface of the first S/D contact stack. The second S/D contact stack includes a second contact trench liner having a second inner side wall extending from a second base portion to an upper surface of the second S/D contact stack. The first inner sidewall directly contacts the second inner sidewall.

Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

Abstract: A first dielectric layer on a substrate is provided. The first dielectric layer has a first level metal line embedded in the dielectric. An opposite gouging feature is created in a top surface of the first level metal line. The opposite gouging feature has a protuberant shape relative to the first level metal line. A second dielectric layer is formed over the first dielectric layer. A compound recess is formed in the second dielectric layer. A first portion of the recess is for a via connector positioned over the opposite gouging feature. A second portion of the recess for a second level metal line. In another aspect of the invention, a device is produced using the method.

Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.

Abstract: A capacitor structure and a method for constructing the structure are described. A metal insulator metal capacitor in an integrated circuit device includes a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is disposed over the extended top face of the bottom capacitor plate. A top capacitor plate is disposed in a top, remainder portion of the trench on top of the high-k dielectric layer.

Abstract: Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect structures, as well as methods for integrating MIM capacitor formation as part of an air gap process flow for fabricating on-chip interconnect structures. For example, a semiconductor device includes a dielectric layer with a first pattern of metal lines and second pattern of metal lines. Air gaps are disposed in spaces between the metal lines. Portions of the spaces between the metal lines of the first pattern of metal lines include a conformal layer of insulating material disposed on sidewalls of the metal lines and metallic material that fills the spaces between the metal lines. The first pattern of metal lines comprises a first capacitor electrode, the metallic fill material comprises a second capacitor electrode, and the conformal layer of insulating material comprises an insulating layer of a MIM capacitor structure.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A method includes selectively forming a silicon-germanium (SiGe) layer on a substrate. At least one SiGe fin with a first width is formed from the SiGe layer. At least one Si fin with a second width is formed from an upper portion of the substrate. The at least one SiGe fin with the first width, the at least one Si fin with the second width and a surface of the substrate below the at least one Si fin are oxidized. The first width of the at least one SiGe fin is condensed in width to a target width.

Abstract: Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

Abstract: A semiconductor structure includes at least one silicon-germanium (SiGe) fin with a first width. The semiconductor structure includes at least one silicon (Si) fin with a second width. An oxide layer isolates the at least one SiGe fin with the first width from a substrate. The at least one SiGe fin with the first width, the at least one Si fin with the second width and a surface of the substrate below the at least one Si fin are each oxidized.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner.

Abstract: A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner.

Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.