Patents by Inventor Theodorus Eduardus Standaert
Theodorus Eduardus Standaert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9269629Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).Type: GrantFiled: October 30, 2014Date of Patent: February 23, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Patent number: 9252242Abstract: Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.Type: GrantFiled: March 25, 2013Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Theodorus Eduardus Standaert, Kangguo Cheng, Junjun Li, Balasubramanian Pranatharthi Haran, Shom Ponoth, Tenko Yamashita
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Patent number: 9219068Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.Type: GrantFiled: October 31, 2014Date of Patent: December 22, 2015Assignee: GLOBALFOUNDRIES INCInventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Publication number: 20150340288Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.Type: ApplicationFiled: October 31, 2014Publication date: November 26, 2015Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Patent number: 9082873Abstract: A structure and method for fabricating finFETs of varying effective device widths is disclosed. Groups of fins are shortened by a predetermined amount to achieve an effective device width that is equivalent to a real (non-integer) number of full-sized fins. The bottom of each group of fins is coplanar, while the tops of the fins from the different groups of fins may be at different levels.Type: GrantFiled: September 20, 2012Date of Patent: July 14, 2015Assignee: International Business Machines CorporationInventors: Tenko Yamashita, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert
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Patent number: 9000522Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.Type: GrantFiled: January 9, 2013Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Publication number: 20150061040Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.Type: ApplicationFiled: November 11, 2014Publication date: March 5, 2015Inventors: Marc Adam Bergendahl, Kangguo Cheng, David Vaclav Horak, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Chih-Chao Yang, Charles William Koburger, III, Xiuyu Cai, Ruilong Xie
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Publication number: 20150064874Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).Type: ApplicationFiled: October 30, 2014Publication date: March 5, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Publication number: 20150064855Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.Type: ApplicationFiled: October 31, 2014Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Publication number: 20150054082Abstract: Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.Type: ApplicationFiled: October 31, 2014Publication date: February 26, 2015Applicant: Intemational Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian Pranatharthi Haran, Junjun Li, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Patent number: 8946792Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).Type: GrantFiled: November 26, 2012Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Patent number: 8941156Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.Type: GrantFiled: January 7, 2013Date of Patent: January 27, 2015Assignees: International Business Machines Corporation, GlobalFoundries, Inc.Inventors: Marc Adam Bergendahl, Kangguo Cheng, David Vaclav Horak, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Chih-Chao Yang, Charles William Koburger, III, Xiuyu Cai, Ruilong Xie
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Publication number: 20140284717Abstract: Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.Type: ApplicationFiled: March 25, 2013Publication date: September 25, 2014Applicant: International Business Machines CorporationInventors: Theodorus Eduardus Standaert, Kangguo Cheng, Junjun Li, Balasubramanian Pranatharthi Haran, Shom Ponoth, Tenko Yamashita
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Patent number: 8835250Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.Type: GrantFiled: September 13, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Jonathan E. Faltermeier, Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Eduardus Standaert
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Publication number: 20140191321Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Publication number: 20140191296Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.Type: ApplicationFiled: January 7, 2013Publication date: July 10, 2014Applicants: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marc Adam Bergendahl, Kangguo Cheng, David Vaclav Horak, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Chih-Chao Yang, Charles William Koburger, III, Xiuyu Cai, Ruilong Xie
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Publication number: 20140191319Abstract: A diode for integration with finFET devices is disclosed. An in-situ doped epitaxial silicon region is grown on the cathode or anode of the diode to increase the surface area of the junction and overall silicon volume for improved heat dissipation during an ESD event.Type: ApplicationFiled: January 4, 2013Publication date: July 10, 2014Applicants: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Shom Ponoth, Balasubramanian Pranatharthiharan, Theodorus Eduardus Standaert, Tenko Yamashita, Robert J. Miller
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Patent number: 8748252Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.Type: GrantFiled: November 26, 2012Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Effendi Leobandung, William Cote, Laertis Economikos, Young-Hee Kim, Dae-Gyu Park, Theodorus Eduardus Standaert, Kenneth Jay Stein, YS Suh, Min Yang
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Publication number: 20140148003Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Effendi Leobandung, William Cote, Laertis Economikos, Young-Hee Kim, Dae-Gyu Park, Theodorus Eduardus Standaert, Kenneth Jay Stein, YS Suh, Min Yang
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Publication number: 20140145248Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita