Patents by Inventor Theodorus Eduardus Standaert
Theodorus Eduardus Standaert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140077296Abstract: A structure and method for fabricating finFETs of varying effective device widths is disclosed. Groups of fins are shortened by a predetermined amount to achieve an effective device width that is equivalent to a real (non-integer) number of full-sized fins. The bottom of each group of fins is coplanar, while the tops of the fins from the different groups of fins may be at different levels.Type: ApplicationFiled: September 20, 2012Publication date: March 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tenko Yamashita, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert
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Publication number: 20140070294Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.Type: ApplicationFiled: September 13, 2012Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan E. Faltermeier, Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Eduardus Standaert
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Patent number: 8592263Abstract: A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.Type: GrantFiled: April 26, 2012Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Theodorus Eduardus Standaert, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Tenko Yamashita
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Publication number: 20130285208Abstract: A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.Type: ApplicationFiled: April 26, 2012Publication date: October 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodorus Eduardus Standaert, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Tenko Yamashita
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Patent number: 8569125Abstract: A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged.Type: GrantFiled: November 30, 2011Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Theodorus Eduardus Standaert, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Soon-Cheon Seo, Tenko Yamashita
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Publication number: 20130173214Abstract: A method and test circuit for electrically measuring the critical dimension of a fin of a FinFET is disclosed. The method comprises measuring the resistance of a first gate test structure, measuring the resistance of a second gate test structure, computing a linear equation relating sheet resistance to gate width, computing a Y intercept value of the linear equation to derive an external resistance value, computing a sheet resistance value for the first gate test structure based on the external resistance value, measuring the resistance of a doped fin test structure, and computing a critical dimension of a fin based on the sheet resistance value.Type: ApplicationFiled: January 4, 2012Publication date: July 4, 2013Applicant: International Business Machines CorporationInventors: Tenko Yamashita, Huiming Bu, Effendi Leobandung, Theodorus Eduardus Standaert
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Publication number: 20130134513Abstract: A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodorus Eduardus Standaert, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Soon-Cheon Seo, Tenko Yamashita
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Patent number: 8298948Abstract: A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.Type: GrantFiled: November 6, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, David L. Rath, Sujatha Sankaran, Andrew H. Simon, Theodorus Eduardus Standaert, Chih-Chao Yang
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Patent number: 7943453Abstract: A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.Type: GrantFiled: December 20, 2007Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Bernd Ernst Eduard Kastenmeier, Byoung Hun Lee, Naim Moumen, Theodorus Eduardus Standaert
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Patent number: 7776737Abstract: An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.Type: GrantFiled: August 14, 2008Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Sujatha Sankaran, Andrew H. Simon, Theodorus Eduardus Standaert
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Publication number: 20100038790Abstract: An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.Type: ApplicationFiled: August 14, 2008Publication date: February 18, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Sujatha Sankaran, Andrew H. Simon, Theodorus Eduardus Standaert
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Publication number: 20090159991Abstract: A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Inventors: Bernd Ernst Eduard Kastenmeier, Byoung Hun Lee, Naim Moumen, Theodorus Eduardus Standaert
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Patent number: 7488679Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.Type: GrantFiled: July 31, 2006Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Theodorus Eduardus Standaert, Pegeen M. Davis, John Anthony Fitzsimmons, Stephen Edward Greco, Tze-Man Ko, Naftali Eliahu Lustig, Lee Matthew Nicholson, Sujatha Sankaran
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Publication number: 20080026568Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.Type: ApplicationFiled: July 31, 2006Publication date: January 31, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodorus Eduardus Standaert, Pegeen M. Davis, John Anthony Fitzsimmons, Stephen Edward Greco, Tze-Man Ko, Naftali Eliahu Lustig, Lee Matthew Nicholson, Sujatha Sankaran
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Publication number: 20070232048Abstract: A method and apparatus is provided for fabricating a damascene interconnection. The method begins by forming on a substrate an organosilicate dielectric layer, a capping layer on the organosilicate dielectric layer, and a resist pattern over the capping layer to define a first interconnect opening. The capping layer is etched through the resist pattern using a first etchant. The resist pattern is removed after etching the capping layer. The dielectric layer is etched through the capping layer using a second etchant different from the first etchant to form the first interconnect opening. An interconnection is completed by filling the first interconnect opening with conductive material.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Inventors: Koji Miyata, Sujatha Sankaran, Theodorus Eduardus Standaert, Ricardo Donaton