Patents by Inventor Theodros Yigzaw
Theodros Yigzaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240061741Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.Type: ApplicationFiled: December 26, 2020Publication date: February 22, 2024Inventors: Rajat AGARWAL, Hsing-Min CHEN, Wei P. CHEN, Wei WU, Jing LING, Kuljit S. BAINS, Kjersten E. CRISS, Deep K. BUCH, Theodros YIGZAW, John G. HOLM, Andrew M. RUDOFF, Vaibhav SINGH, Sreenivas MANDAVA
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Publication number: 20230205626Abstract: Multilevel memory error management techniques can improve system performance, availability, and reliability by preventing future accesses to faulty near memory locations. According to examples described herein, multilevel memory error management techniques enable proactively offlining far memory locations mapped to a faulty near memory location before additional faults are encountered, and/or maintaining a faulty near memory location list to enable bypassing the faulty near memory location to prevent future errors.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Inventors: Rubén Salvador HERNÁNDEZ CORTÉS, Gaurav PORWAL, Omar AVELAR SUAREZ, Theodros YIGZAW
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Publication number: 20230091969Abstract: Methods and apparatus relating to lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors are described. In an embodiment, a plurality of storage entries store error information to be detected at one or more physical lanes of an interface. Faulty lane detection logic circuitry determines which of the one or more physical lanes is faulty or more likely to be faulty based at least in part on the stored error information for the one or more physical lanes of the interface. The stored error information comprises historical error details for the one or more physical lanes of the interface. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Applicant: Intel CorporationInventors: Gaurav Porwal, Theodros Yigzaw, Subhankar Panda, John Holm
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Publication number: 20230088947Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Applicant: Intel CorporationInventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Publication number: 20220350500Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.Type: ApplicationFiled: June 30, 2022Publication date: November 3, 2022Inventors: Wei P. CHEN, Theodros YIGZAW, Sarathy JAYAKUMAR, Anthony LUCK, Deep K. BUCH, Rajat AGARWAL, Kuljit S. BAINS, John G. HOLM, Brent CHARTRAND, Keith KLAYMAN
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Publication number: 20220334736Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Applicant: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Hsing-Min Chen, Theodros Yigzaw, Russell Clapp, Saravanan Sethuraman, Patricia Mwove Shaffer
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Publication number: 20220196733Abstract: Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Gaurav Porwal, Subhankar Panda, Theodros Yigzaw, John Holm
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Patent number: 11307996Abstract: In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.Type: GrantFiled: November 30, 2018Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Sarathy Jayakumar, Ashok Raj, Wei P. Chen, Theodros Yigzaw, John Holm
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Patent number: 11182313Abstract: In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.Type: GrantFiled: May 29, 2019Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Ishwar Agarwal, Theodros Yigzaw
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Publication number: 20210318932Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Applicant: Intel CorporationInventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Publication number: 20210286667Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to provide management of a connected hardware subsystem with respect to one or more of reliability, availability and serviceability, and coordinate the management of the connected hardware subsystem with respect to one or more of reliability, availability and serviceability between the connected hardware subsystem and a host. Other embodiments are disclosed and claimed.Type: ApplicationFiled: May 27, 2021Publication date: September 16, 2021Applicant: Intel CorporationInventors: Theodros Yigzaw, John Holm, Subhankar Panda, Hugo Enrique Gonzalez Chavero, Satyaprakash Nanda, Omar Avelar Suarez, Guarav Porwal
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Publication number: 20210248026Abstract: Techniques and mechanisms for a processor to efficiently identify a circuit resource as being a source of data poisoning. In an embodiment, metadata is communicated, in association with a communication of poisoned data to which the metadata pertains, to a first circuit block of a processor. The metadata indicates a poisoned state of the data, wherein the metadata identifies a second circuit block—which is included in or coupled to the processor—as being a poisoner of the data. Based on the metadata, the first circuit block generates a fault message which identifies the second circuit block as the poisoner of the data. In another embodiment, the processor further comprises the second circuit block, which poisons the data (based on the detection of an error condition) by providing in the metadata a unique identifier which is assigned to the second circuit block.Type: ApplicationFiled: January 20, 2021Publication date: August 12, 2021Inventors: Mohan J. Kumar, Theodros Yigzaw, Murugasamy Nachimuthu, Ashok Raj, Jose Vargas
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Patent number: 11068339Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.Type: GrantFiled: May 20, 2019Date of Patent: July 20, 2021Assignee: Intel CorporationInventors: Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu Ghetie, Mohan J. Kumar, Theodros Yigzaw, Sarathy Jayakumar, Neeraj S. Upasani
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Patent number: 11048587Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: GrantFiled: March 4, 2019Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Patent number: 10929232Abstract: A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.Type: GrantFiled: May 31, 2017Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Subhankar Panda, Sarathy Jayakumar, Gaurav Porwal, Theodros Yigzaw
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Publication number: 20200201700Abstract: Techniques and mechanisms for a processor to efficiently identify a circuit resource as being a source of data poisoning. In an embodiment, metadata is communicated, in association with a communication of poisoned data to which the metadata pertains, to a first circuit block of a processor. The metadata indicates a poisoned state of the data, wherein the metadata identifies a second circuit block—which is included in or coupled to the processor—as being a poisoner of the data. Based on the metadata, the first circuit block generates a fault message which identifies the second circuit block as the poisoner of the data. In another embodiment, the processor further comprises the second circuit block, which poisons the data (based on the detection of an error condition) by providing in the metadata a unique identifier which is assigned to the second circuit block.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Applicant: Intel CorporationInventors: Mohan J. Kumar, Theodros Yigzaw, Murugasamy Nachimuthu, Ashok Raj, Jose Vargas
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Publication number: 20200174943Abstract: In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: Sarathy Jayakumar, Ashok Raj, Wei P. Chen, Theodros Yigzaw, John Holm
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Publication number: 20200004633Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: ApplicationFiled: March 4, 2019Publication date: January 2, 2020Inventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Publication number: 20190278721Abstract: In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.Type: ApplicationFiled: May 29, 2019Publication date: September 12, 2019Inventors: Ishwar Agarwal, Theodros Yigzaw
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Publication number: 20190272214Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.Type: ApplicationFiled: May 20, 2019Publication date: September 5, 2019Inventors: Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu Ghetie, Mohan J. Kumar, Theodros Yigzaw, Sarathy Jayakumar, Neeraj S. Upasani