Patents by Inventor Thierry Barge

Thierry Barge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210121103
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Application
    Filed: January 4, 2021
    Publication date: April 29, 2021
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Publication number: 20210075389
    Abstract: A process for fabricating a substrate for a radiofrequency device by joining a piezoelectric layer to a carrier substrate by way of an electrically insulating layer, the piezoelectric layer having a rough surface at its interface with the electrically insulating layer, the process being characterized in that it comprises the following steps: —providing a piezoelectric substrate having a rough surface for reflecting a radiofrequency wave, —depositing a dielectric layer on the rough surface of the piezoelectric substrate, —providing a carrier substrate, —depositing a photo-polymerizable adhesive layer on the carrier substrate, —bonding the piezoelectric substrate to the carrier substrate by way of the dielectric layer and of the adhesive layer, in order to form an assembled substrate, —irradiating the assembled substrate with a light flux in order to polymerize the adhesive layer, the adhesive layer and the dielectric layer together forming the electrically insulating layer.
    Type: Application
    Filed: March 26, 2019
    Publication date: March 11, 2021
    Inventors: Djamel Belhachemi, Thierry Barge
  • Patent number: 10943778
    Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: March 9, 2021
    Assignee: Soitec
    Inventors: Pascal Guenard, Marcel Broekaart, Thierry Barge
  • Publication number: 20210066063
    Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.
    Type: Application
    Filed: November 11, 2020
    Publication date: March 4, 2021
    Inventors: Pascal Guenard, Marcel Broekaart, Thierry Barge
  • Patent number: 10924081
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: February 16, 2021
    Assignee: Soitec
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Publication number: 20210020826
    Abstract: A method for transferring a piezoelectric layer onto a support substrate comprises:—providing a donor substrate including a heterostructure comprising a piezoelectric substrate bonded to a handling substrate, and a polymerized adhesive layer at the interface between the piezoelectric substrate and the handling substrate,—forming a weakened zone in the piezoelectric substrate, so as to delimit the piezoelectric layer to be transferred,—providing the support substrate,—forming a dielectric layer on a main face of the support substrate and/or of the piezoelectric substrate,—bonding the donor substrate to the support substrate, the dielectric layer being at the bonding interface, and—fracturing and separating the donor substrate along the weakened zone at a temperature below or equal to 300° C.
    Type: Application
    Filed: March 21, 2019
    Publication date: January 21, 2021
    Applicant: Soitec
    Inventors: Djamel Belhachemi, Thierry Barge
  • Publication number: 20200228088
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Patent number: 10608610
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 31, 2020
    Assignee: Soitec
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Publication number: 20190088462
    Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.
    Type: Application
    Filed: July 13, 2016
    Publication date: March 21, 2019
    Applicants: Soitec, Soitec
    Inventors: Pascal Guenard, Marcel Broekaart, Thierry Barge
  • Publication number: 20190007024
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Application
    Filed: December 21, 2016
    Publication date: January 3, 2019
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Patent number: 9812371
    Abstract: The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of the substrate by ion bombardment, wherein a plasma of a supplied gas is generated, and a bombardment energy of the ions in the plasma is controlled by a radio frequency electromagnetic field. The bombardment energy of the ions is higher than a first threshold so as to tear the metal contamination from the surface of the substrate, and the bombardment energy of the ions is lower than a second threshold so as to prevent a surface quality degradation of the surface of the substrate.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 7, 2017
    Assignee: Soitec
    Inventor: Thierry Barge
  • Publication number: 20160284608
    Abstract: The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of the substrate by ion bombardment, wherein a plasma of a supplied gas is generated, and a bombardment energy of the ions in the plasma is controlled by a radio frequency electromagnetic field. The bombardment energy of the ions is higher than a first threshold so as to tear the metal contamination from the surface of the substrate, and the bombardment energy of the ions is lower than a second threshold so as to prevent a surface quality degradation of the substrate surface.
    Type: Application
    Filed: March 23, 2016
    Publication date: September 29, 2016
    Inventor: Thierry Barge
  • Patent number: 8232130
    Abstract: The invention relates to a process of bonding by molecular adhesion of two layers, such as wafers of semiconductor material, wherein propagation of a first bonding wave is initiated from a pressure point applied to at least one of the two layers, and wherein the first bonding wave step is followed by propagating a second bonding wave over an area, for example, in the vicinity of the pressure point. Propagation of the second bonding wave may be obtained through the interposing of a separation element between the two wafers and the withdrawal of the element, for example, after the beginning of the first bonding wave propagation.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: July 31, 2012
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Marcel Broekaart, Bernard Aspar, Thierry Barge, Chrystelle L. Blanchard
  • Patent number: 8158487
    Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: April 17, 2012
    Assignee: Soitec
    Inventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
  • Publication number: 20110183495
    Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 28, 2011
    Inventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
  • Patent number: 7648888
    Abstract: The invention relates to a method of splitting apart a substrate of two adjoining wafers defining between them a cleavage plane, by bringing each substrate into a substrate-receiving space; and clamping first and second jaw portions onto each substrate in such a manner as to hold each substrate and urge apart the two wafers of each substrate by co-operation between the shapes of housings in first and second portions of the two jaws, respectively. The invention also relates to a splitting method that includes bringing each substrate into a substrate-reception space; clamping together separator portions onto each substrate so as to split apart the two wafers of each substrate; and clamping the split-apart substrate wafers so as to hold the wafers together. An automated system for processing multiple substrates is also provided.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: January 19, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
  • Publication number: 20090280595
    Abstract: The invention relates to a process of bonding by molecular adhesion of two layers, such as wafers of semiconductor material, wherein propagation of a first bonding wave is initiated from a pressure point applied to at least one of the two layers, and wherein the first bonding wave step is followed by propagating a second bonding wave over an area, for example, in the vicinity of the pressure point. Propagation of the second bonding wave may be obtained through the interposing of a separation element between the two wafers and the withdrawal of the element, for example, after the beginning of the first bonding wave propagation.
    Type: Application
    Filed: August 21, 2008
    Publication date: November 12, 2009
    Applicant: S.O.I. TEC Silicon on Insulator Technologies
    Inventors: Marcel Broekaart, Bernard Aspar, Thierry Barge, Chrystelle L. Blanchard
  • Patent number: 7406994
    Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member maintains the position of the substrate on a moveable support. A cutting mechanism having at least one blade is provided for contacting the substrate and inducing a cleaving wave therein. The cutting mechanism is operatively associated with the positioning member so that the as at least one blade contacts the annular notch, the positioning member prevents movement of the substrate and the moveable support moves away from the substrate to allow the cleaving wave to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: August 5, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cécile Berne, Olivier Rayssac
  • Patent number: 7288418
    Abstract: A process for treating substrates for the microelectronics or optoelectronics industry, wherein the substrates include on at least one of their faces a working layer in which components are intended to be formed. The process includes a step of annealing under a reductive atmosphere followed by a step of chemical-mechanical polishing on the free surface of the working layer.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: October 30, 2007
    Assignee: S.O.O.Tec Silicon on Insulator Technologies
    Inventors: Thierry Barge, André Auberton-Herve, Hiroji Aga, Naoto Tate
  • Patent number: 7235427
    Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: June 26, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani