Patents by Inventor Thierry Barge
Thierry Barge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8232130Abstract: The invention relates to a process of bonding by molecular adhesion of two layers, such as wafers of semiconductor material, wherein propagation of a first bonding wave is initiated from a pressure point applied to at least one of the two layers, and wherein the first bonding wave step is followed by propagating a second bonding wave over an area, for example, in the vicinity of the pressure point. Propagation of the second bonding wave may be obtained through the interposing of a separation element between the two wafers and the withdrawal of the element, for example, after the beginning of the first bonding wave propagation.Type: GrantFiled: August 21, 2008Date of Patent: July 31, 2012Assignee: S.O.I.TEC Silicon on Insulator TechnologiesInventors: Marcel Broekaart, Bernard Aspar, Thierry Barge, Chrystelle L. Blanchard
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Patent number: 8158487Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.Type: GrantFiled: January 21, 2011Date of Patent: April 17, 2012Assignee: SoitecInventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
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Publication number: 20110183495Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.Type: ApplicationFiled: January 21, 2011Publication date: July 28, 2011Inventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
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Patent number: 7648888Abstract: The invention relates to a method of splitting apart a substrate of two adjoining wafers defining between them a cleavage plane, by bringing each substrate into a substrate-receiving space; and clamping first and second jaw portions onto each substrate in such a manner as to hold each substrate and urge apart the two wafers of each substrate by co-operation between the shapes of housings in first and second portions of the two jaws, respectively. The invention also relates to a splitting method that includes bringing each substrate into a substrate-reception space; clamping together separator portions onto each substrate so as to split apart the two wafers of each substrate; and clamping the split-apart substrate wafers so as to hold the wafers together. An automated system for processing multiple substrates is also provided.Type: GrantFiled: January 24, 2006Date of Patent: January 19, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
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Publication number: 20090280595Abstract: The invention relates to a process of bonding by molecular adhesion of two layers, such as wafers of semiconductor material, wherein propagation of a first bonding wave is initiated from a pressure point applied to at least one of the two layers, and wherein the first bonding wave step is followed by propagating a second bonding wave over an area, for example, in the vicinity of the pressure point. Propagation of the second bonding wave may be obtained through the interposing of a separation element between the two wafers and the withdrawal of the element, for example, after the beginning of the first bonding wave propagation.Type: ApplicationFiled: August 21, 2008Publication date: November 12, 2009Applicant: S.O.I. TEC Silicon on Insulator TechnologiesInventors: Marcel Broekaart, Bernard Aspar, Thierry Barge, Chrystelle L. Blanchard
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Patent number: 7406994Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member maintains the position of the substrate on a moveable support. A cutting mechanism having at least one blade is provided for contacting the substrate and inducing a cleaving wave therein. The cutting mechanism is operatively associated with the positioning member so that the as at least one blade contacts the annular notch, the positioning member prevents movement of the substrate and the moveable support moves away from the substrate to allow the cleaving wave to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.Type: GrantFiled: January 30, 2007Date of Patent: August 5, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cécile Berne, Olivier Rayssac
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Patent number: 7288418Abstract: A process for treating substrates for the microelectronics or optoelectronics industry, wherein the substrates include on at least one of their faces a working layer in which components are intended to be formed. The process includes a step of annealing under a reductive atmosphere followed by a step of chemical-mechanical polishing on the free surface of the working layer.Type: GrantFiled: February 7, 2006Date of Patent: October 30, 2007Assignee: S.O.O.Tec Silicon on Insulator TechnologiesInventors: Thierry Barge, André Auberton-Herve, Hiroji Aga, Naoto Tate
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Patent number: 7235427Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.Type: GrantFiled: February 24, 2005Date of Patent: June 26, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani
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Publication number: 20070122926Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member maintains the position of the substrate on a moveable support. A cutting mechanism having at least one blade is provided for contacting the substrate and inducing a cleaving wave therein. The cutting mechanism is operatively associated with the positioning member so that the as at least one blade contacts the annular notch, the positioning member prevents movement of the substrate and the moveable support moves away from the substrate to allow the cleaving wave to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.Type: ApplicationFiled: January 30, 2007Publication date: May 31, 2007Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cecile Berne, Olivier Rayssac
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Patent number: 7189304Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The cutting device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch that is located below the weakened area. The positioning member maintains a predetermined position of the substrate on a support. The device also includes cutting means having at least one blade for contacting the substrate and for inducing a cleaving wave into the substrate. The cutting means is operatively associated with the positioning member so that the at least one blade contacts the annular notch and the positioning member prevents movement of the substrate. The at least one blade induces a cleaving wave of sufficient intensity to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.Type: GrantFiled: October 7, 2003Date of Patent: March 13, 2007Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cécile Berne, Olivier Rayssac
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Publication number: 20060189102Abstract: A process for treating substrates for the microelectronics or optoelectronics industry, wherein the substrates include on at least one of their faces a working layer in which components are intended to be formed. The process includes a step of annealing under a reductive atmosphere followed by a step of chemical-mechanical polishing on the free surface of the working layer.Type: ApplicationFiled: February 7, 2006Publication date: August 24, 2006Inventors: Thierry Barge, Andre Auberton-Herve, Hiroji Aga, Naoto Tate
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Publication number: 20060138189Abstract: The invention relates to a method of splitting apart a substrate of two adjoining wafers defining between them a cleavage plane, by bringing each substrate into a substrate-receiving space; and clamping first and second jaw portions onto each substrate in such a manner as to hold each substrate and urge apart the two wafers of each substrate by co-operation between the shapes of housings in first and second portions of the two jaws, respectively. The invention also relates to a splitting method that includes bringing each substrate into a substrate-reception space; clamping together separator portions onto each substrate so as to split apart the two wafers of each substrate; and clamping the split-apart substrate wafers so as to hold the wafers together. An automated system for processing multiple substrates is also provided.Type: ApplicationFiled: January 24, 2006Publication date: June 29, 2006Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A., a French companyInventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
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Method for treating substrates for microelectronics and substrates obtained according to said method
Patent number: 7029993Abstract: The invention relates to a method for treating substrates (50) for microelectronics or optoelectronics, whereby said substrates comprise a useful layer (52) on at least one of the surfaces thereof. The inventive method includes a mechanical/chemical polishing step occurring on a bare surface (54) of the useful layer and is characterized in that it also comprises a post-curing step in a reductive atmosphere (100) before said polishing step occurs.Type: GrantFiled: August 17, 2000Date of Patent: April 18, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Thierry Barge, André Auberton-Herve, Hiroji Aga, Naoto Tate -
Patent number: 7017570Abstract: The invention provides an apparatus for splitting a substrate apart, the substrate comprising two adjoining wafers defining between them a cleavage plane, the apparatus being characterized in that it comprises: means for feeding splitter means with a plurality of substrates disposed in a substrate-storage direction; splitter means for splitting apart wafers of the substrates, the splitter means comprising moving jaws; and means for performing controlled displacement of certain substrate wafers after they have been split apart in a direction that is substantially parallel to the substrate-storage direction, whereby the apparatus is suitable for splitting apart the plurality of substrates. The invention also provides an associated splitting method.Type: GrantFiled: February 9, 2004Date of Patent: March 28, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
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Publication number: 20050208322Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.Type: ApplicationFiled: February 24, 2005Publication date: September 22, 2005Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A.Inventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani
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Patent number: 6902988Abstract: The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising: a first sacrificial oxidation stage for removing material constituting the working layer (6) over a certain surface thickness of each substrate (1), a stage of polishing (200) the face which has been subjected to the first sacrificial oxidation stage (100), and a second sacrificial oxidation stage for again removing material constituting the working layer (6) on the polished face (17).Type: GrantFiled: December 13, 2002Date of Patent: June 7, 2005Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani
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Publication number: 20040188487Abstract: The invention provides an apparatus for splitting a substrate apart, the substrate comprising two adjoining wafers defining between them a cleavage plane, the apparatus being characterized in that it comprises:Type: ApplicationFiled: February 9, 2004Publication date: September 30, 2004Inventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
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Publication number: 20040144487Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The cutting device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch that is located below the weakened area. The positioning member maintains a predetermined position of the substrate on a support. The device also includes cutting means having at least one blade for contacting the substrate and for inducing a cleaving wave into the substrate. The cutting means is operatively associated with the positioning member so that the at least one blade contacts the annular notch and the positioning member prevents movement of the substrate. The at least one blade induces a cleaving wave of sufficient intensity to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.Type: ApplicationFiled: October 7, 2003Publication date: July 29, 2004Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cecile Berne, Olivier Rayssac
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Publication number: 20040115905Abstract: The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising:Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Inventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani
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Patent number: 6720640Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.Type: GrantFiled: May 29, 2003Date of Patent: April 13, 2004Assignees: Shin-Etsu Handotai Co., Ltd., S.O.I. Tec Silicon on Insulator TechnologiesInventors: Susumu Kuwabara, Kiyoshi Mitani, Naoto Tate, Masatake Nakano, Thierry Barge, Christophe Maleville