Abstract: A method for producing nanostructures having a metal oxide shell, carried by a top face of a substrate whose greatest dimension is greater than or equal to 100 mm by MOCVD metalorganic chemical vapour deposition, including successive steps carried out in a reactor configured for MOCVD deposition of nucleation and growth. The nucleation step includes forming non-contiguous metal nuclei by depositing a metal by MOCVD using a metalorganic precursor on the top face of the substrate and oxidising the metal of the metal nuclei, to form oxidised nuclei and ensure stabilisation of the nuclei. The growth step includes depositing a metal by MOCVD using the metalorganic precursor, to form non-contiguous nanostructures by growth of the oxidised nanostructures, and oxidising the deposited metal of the nanostructures formed in the nucleation to form oxidised nanostructures.

Abstract: A method for producing, on a structure based on a material III-V, of a dielectric layer, the method comprising producing a first dielectric film by ALD by carrying out a plurality of first cycles, each comprising at least: one injection in the reaction chamber of a precursor based on a first material and one injection in the reaction chamber of a water or ozone-based precursor; and producing, on the first dielectric film, a second dielectric film by plasma-enhanced ALD by carrying out a plurality of second cycles, each comprising at least: one injection in the reaction chamber of a precursor based on a second material and one injection in the reaction chamber of an oxygen or nitrogen based precursor.

Abstract: A process for the hetero-integration of a semiconductor material of interest on a silicon substrate, includes a step of structuring the substrate which comprises a step of producing a growth mask on the surface of the silicon substrate, the growth mask comprising a plurality of masking patterns, two masking patterns being separated by a trench wherein the silicon substrate is exposed; a step of forming a two-dimensional buffer layer made of a 2D material, the buffer layer being free of side bonds on its free surface and being formed selectively on at least one silicon plane of [111] orientation in at least one trench, the step of forming a buffer layer being performed after the structuring step; a step of forming at least one layer of a semiconductor material of interest on the buffer layer. The semiconductor material of interest is preferably a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

Abstract: A method for producing an aluminium nitride (AlN)-based layer on a structure with the basis of silicon (Si) or with the basis of a III-V material, may include several deposition cycles performed in a plasma reactor comprising a reaction chamber inside which is disposed a substrate having the structure. Each deposition cycle may include at least the following: deposition of aluminium-based species on an exposed surface of the structure, the deposition including at least one injection into the reaction chamber of an aluminium (Al)-based precursor; and nitridation of the exposed surface of the structure, the nitridation including at least one injection into the reaction chamber of a nitrogen (N)-based precursor and the formation in the reaction chamber of a nitrogen-based plasma. During the formation of the nitrogen-based plasma, a non-zero polarisation voltage Vbias_substrate may be applied to the substrate.

Abstract: A process for epitaxying GaSe on a [111]-oriented silicon substrate, includes a step of selecting a [111]-oriented silicon substrate resulting from cutting a silicon bar in a miscut direction which is one of the three [11-2] crystallographic directions, the miscut angle (?) being smaller than or equal to 0.

Abstract: A process for the hetero-integration of a semiconductor material of interest on a silicon substrate, includes a step of structuring the substrate which comprises a step of producing a growth mask on the surface of the silicon substrate, the growth mask comprising a plurality of masking patterns, two masking patterns being separated by a trench wherein the silicon substrate is exposed; a step of forming a two-dimensional buffer layer made of a 2D material, the buffer layer being free of side bonds on its free surface and being formed selectively on at least one silicon plane of [111] orientation in at least one trench, the step of forming a buffer layer being performed after the structuring step; a step of forming at least one layer of a semiconductor material of interest on the buffer layer. The semiconductor material of interest is preferably a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

Abstract: A process for epitaxying GaSe on a [111]-oriented silicon substrate, includes a step of selecting a [111]-oriented silicon substrate resulting from cutting a silicon bar in a miscut direction which is one of the three [11-2] crystallographic directions, the miscut angle (?) being smaller than or equal to 0.

Abstract: A method for producing a network of nanostructures from at least one semiconductor material, including a step of forming nanostructures on the surface of a substrate, at least a part of the nanostructures having areas of contact between each other, comprising, in sequence and after the step of forming: a step of deoxidising the surface of the nanostructures and a step of reinforcing the bond between the nanostructures at the contact areas.

Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.

Abstract: A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by: forming a crystalline buffer layer situated at least partly in the trench in the masking layer, extending from the substrate and forming a projection beyond the masking layer so that an upper part of the lateral flanks of said buffer layer is left uncovered, the formation step comprising a growth of the buffer layer from the substrate, and forming a crystalline epitaxial layer in a second material, different from the material of the buffer layer, by growth from said upper part of the lateral flanks of the buffer layer left uncovered.

Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.

Abstract: A material (M) includes a substrate one of the surfaces of which is covered with a layer based on a block copolymer having a block (B) consisting of a polysaccharide and to its uses for electronics, in order to prepare organic electroluminescent diodes (OLEDs) or organic photovoltaic cells (OPV) or for designing detection devices (nanobiosensors, biochips).

Abstract: A method for producing a network of nanostructures from at least one semiconductor material, including a step of forming nanostructures on the surface of a substrate, at least a part of the nanostructures having areas of contact between each other, comprising, in sequence and after the step of forming: a step of deoxidising the surface of the nanostructures and a step of reinforcing the bond between the nanostructures at the contact areas.

Abstract: A method for fabricating patterns of III-V semiconductor material on a semiconductor substrate based on oriented silicon or germanium comprises: production of a growth mask on the surface of the substrate, defining masking patterns Miox of width L, of height hox with a distance S between masking patterns; growth of patterns MiIII-V of III-V material between said masking patterns, such that said patterns exhibit a height h relative to the top plane of said masking patterns, said height h being at or above a critical minimum height hc, the growth step comprising: determining growth rates v100 and v110 at right angles to the face of the III-V material, defining ratio R=v100/v110; determining the angle of dislocations ? of the III-V material relative to the plane of the substrate; determining the critical minimum height hc by the equation: h c = h ox - S × tan ? ( ? ) tan ? ( ? ) R - 1 with R being determined to be greater than tan(?).

Abstract: A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by: forming a crystalline buffer layer situated at least partly in the trench in the masking layer, extending from the substrate and forming a projection beyond the masking layer so that an upper part of the lateral flanks of said buffer layer is left uncovered, the formation step comprising a growth of the buffer layer from the substrate, and forming a crystalline epitaxial layer in a second material, different from the material of the buffer layer, by growth from said upper part of the lateral flanks of the buffer layer left uncovered.

Abstract: A method for fabricating patterns of III-V semiconductor material on a semiconductor substrate based on oriented silicon or germanium comprises: production of a growth mask on the surface of the substrate, defining masking patterns Miox of width L, of height hox with a distance S between masking patterns; growth of patterns MiIII-V of III-V material between said masking patterns, such that said patterns exhibit a height h relative to the top plane of said masking patterns, said height h being at or above a critical minimum height hc, the growth step comprising: determining growth rates v100 and v110 at right angles to the face of the III-V material, defining ratio R=v100/v110; determining the angle of dislocations ? of the III-V material relative to the plane of the substrate; determining the critical minimum height hc by the equation: h c = h ox - S × tan ? ( ? ) tan ? ( ? ) R - 1 with R being determined to be greater than tan(?).

Abstract: A process for obtaining an array of nanodots (212) for microelectronic devices, characterized in that it comprises the following steps: deposition of a silicon layer (210) on a substrate (100, 132), formation, above the silicon layer (210), of a layer (240) of a material capable of self-organizing, in which at least one polymer substantially forms cylinders (242) organized into an array within a matrix (244), formation of patterns (243) in the layer (240) of a material capable of self-organizing by elimination of the said cylinders (242), formation of a hard mask (312) by transfer of the said patterns (243), production of silicon dots (212) in the silicon layer (210) by engraving through the hard mask (312), silicidation of the silicon dots (212), comprising deposition of a metal layer (510).

Abstract: A method for making a crossbar array of crossed conductive or semi-conductive access lines on a substrate, the crossbar array including on a crossbar array insulator, in a plane parallel to the substrate, a first level of lines including a plurality of first lines parallel with each other made of a conductive or semi-conductive material; on the first level of lines, a second level of lines including a plurality of second lines parallel with each other made of a conductive or semi-conductive material, the second lines being substantially perpendicular to the first lines. The method includes forming, on the substrate, a first cavity of substantially rectangular shape; forming a second cavity of substantially rectangular shape superimposed to the first cavity, the first and second cavities intersecting each other perpendicularly so as to form a resultant cavity.

Abstract: The transistor (100) comprises a nanowire (101) at least partially forming a channel of the transistor (100), a source contact (102) arranged at a first longitudinal end (103) of the nanowire (101), a drain contact (104) arranged at a second longitudinal end (105) of the nanowire (101), and a gate (106) arranged on the nanowire (101) between the source contact (102) and the drain contact (104). Furthermore, a portion of the gate (106) covers, with the interposition of a dielectric material (107), a corresponding portion of the source contact (102) and/or of the drain contact (104) arranged along the nanowire (101) between its two longitudinal ends (103, 105).

Abstract: A process of making a microelectronic light-emitting device, including: a) growth on a metallic support of multiple wires based on one or more semi-conducting materials designed to emit radiant light, and b) formation of at least one electrical conducting zone of contact on at least one of the wires.