Patents by Inventor Thierry Soude

Thierry Soude has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200371541
    Abstract: An electronic device includes a starting circuit configured to compare a value representative of the power supply voltage with a threshold, wherein the circuit includes a generator of a current proportional to temperature.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 26, 2020
    Inventors: Jimmy Fort, Maud Pierrel, Nicolas Borrel, Thierry Soude
  • Patent number: 10685923
    Abstract: An electronic chip including a plurality of buried doped bars and a circuit for detecting an anomaly of an electric characteristic of the bars.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 16, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Jimmy Fort, Thierry Soude
  • Publication number: 20180261560
    Abstract: An electronic chip including a plurality of buried doped bars and a circuit for detecting an anomaly of an electric characteristic of the bars.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 13, 2018
    Inventors: Alexandre SARAFIANOS, Jimmy FORT, Thierry SOUDE
  • Patent number: 10054973
    Abstract: A method for smoothing current consumed by an electronic device is based on a series of current copying operations and on a current source delivering a reference current. The reference current is delivered in such a manner that current consumed as seen from the power supply depends on the reference current.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: August 21, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas Demange, Jimmy Fort, Thierry Soude
  • Patent number: 9836070
    Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: December 5, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Patent number: 9804631
    Abstract: A circuit includes a first PMOS transistor that includes a first PMOS source coupled to a first input node, a first PMOS gate, and a first PMOS drain. A second PMOS transistor includes a second PMOS source coupled to a second input node, a second PMOS gate, and a second PMOS drain coupled to the second PMOS gate. A first resistor coupled between the first PMOS source and a ground node. A first diode element coupled between the first resistor and the ground node and a second diode element coupled between the second PMOS source and the ground node. A third PMOS transistor includes a third PMOS gate, a third PMOS source coupled to a supply node, and a third PMOS drain coupled to the first input node. A fourth PMOS transistor includes a fourth PMOS gate coupled to the third PMOS gate, a fourth PMOS source coupled to the supply node, and a fourth PMOS drain coupled to the second input node.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 31, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Publication number: 20170192448
    Abstract: A method for smoothing current consumed by an electronic device is based on a series of current copying operations and on a current source delivering a reference current. The reference current is delivered in such a manner that current consumed as seen from the power supply depends on the reference current.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 6, 2017
    Inventors: Nicolas DEMANGE, Jimmy Fort, Thierry Soude
  • Patent number: 9678525
    Abstract: A method for smoothing current consumed by an electronic device is based on a series of current copying operations and on a current source delivering a reference current. The reference current is delivered in such a manner that current consumed as seen from the power supply depends on the reference current.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: June 13, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas Demange, Jimmy Fort, Thierry Soude
  • Publication number: 20170097653
    Abstract: A method for smoothing current consumed by an electronic device is based on a series of current copying operations and on a current source delivering a reference current. The reference current is delivered in such a manner that current consumed as seen from the power supply depends on the reference current.
    Type: Application
    Filed: May 10, 2016
    Publication date: April 6, 2017
    Inventors: Nicolas DEMANGE, Jimmy FORT, Thierry SOUDE
  • Publication number: 20160357213
    Abstract: A circuit includes a first PMOS transistor that includes a first PMOS source coupled to a first input node, a first PMOS gate, and a first PMOS drain. A second PMOS transistor includes a second PMOS source coupled to a second input node, a second PMOS gate, and a second PMOS drain coupled to the second PMOS gate. A first resistor coupled between the first PMOS source and a ground node. A first diode element coupled between the first resistor and the ground node and a second diode element coupled between the second PMOS source and the ground node. A third PMOS transistor includes a third PMOS gate, a third PMOS source coupled to a supply node, and a third PMOS drain coupled to the first input node. A fourth PMOS transistor includes a fourth PMOS gate coupled to the third PMOS gate, a fourth PMOS source coupled to the supply node, and a fourth PMOS drain coupled to the second input node.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Jimmy Fort, Thierry Soude
  • Patent number: 9454163
    Abstract: According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Generating the adjustable bandgap reference also includes generating a current inversely proportional to absolute temperature (CTAT), summing the PTAT and the CTAT currents and generating the bandgap reference voltage based on the sum of the currents. Equalizing includes connecting-across the terminals of the core a first fed-back amplifier with at least one first stage arranged as a folded setup and including first PMOS transistors arranged according to a common-gate setup. Equalizing also includes biasing the first stage based on the CTAT current. The summation of the PTAT and CTAT currents is performed in the feedback stage of the first amplifier.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: September 27, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Patent number: 9298202
    Abstract: An adjustable bandgap reference voltage includes a first circuit for generating IPTAT, a second circuit for generating ICTAT, and an output module configured to generate the reference voltage. The first circuit includes a first amplifier connected to terminals of a core for equalizing voltages across the terminals, where the first amplifier has a first stage that is biased by the current inversely proportional to absolute temperature and is arranged according to a folded setup with first PMOS transistors arranged according to a common-gate setup. The first circuit also includes a feedback stage with an input connected to the first amplifier output. The feedback stage output is connected to the first stage input and to a terminal of the core. The second circuit includes a follower amplifier connected to a terminal of the core and separated from the first amplifier and the output module is connected to the feedback stage.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: March 29, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Publication number: 20160062377
    Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 3, 2016
    Inventors: Jimmy Fort, Thierry Soude
  • Patent number: 9190969
    Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 17, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Patent number: 9052345
    Abstract: A system for detecting a laser attack on an integrated circuit chip formed in a semiconductor substrate, including a detection device capable of detecting voltage variations of the substrate. The system includes P-type first wells and N-type second wells extending in a P-type upper portion of the substrate; an N-type buried layer extending under at least a portion of the first and second wells; biasing contacts for the second wells and the buried layer; ground contacts for the first wells; and substrate contacts for detecting a substrate voltage, the detection contacts surrounding the first and second wells. The detection device comprises a resistor having a first terminal connected to said ground contacts of the first wells and a second terminal connected to said substrate contacts; and a comparator connected in with the resistor configured to detect a potential difference across the resistor.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: June 9, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Thierry Soude
  • Publication number: 20150153753
    Abstract: An adjustable bandgap reference voltage includes a first circuit for generating IPTAT, a second circuit for generating ICTAT, and an output module configured to generate the reference voltage. The first circuit includes a first amplifier connected to terminals of a core for equalizing voltages across the terminals, where the first amplifier has a first stage that is biased by the current inversely proportional to absolute temperature and is arranged according to a folded setup with first PMOS transistors arranged according to a common-gate setup. The first circuit also includes a feedback stage with an input connected to the first amplifier output. The feedback stage output is connected to the first stage input and to a terminal of the core. The second circuit includes a follower amplifier connected to a terminal of the core and separated from the first amplifier and the output module is connected to the feedback stage.
    Type: Application
    Filed: February 6, 2015
    Publication date: June 4, 2015
    Inventors: Jimmy Fort, Thierry Soude
  • Publication number: 20150145487
    Abstract: According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Generating the adjustable bandgap reference also includes generating a current inversely proportional to absolute temperature (CTAT), summing the PTAT and the CTAT currents and generating the bandgap reference voltage based on the sum of the currents. Equalizing includes connecting-across the terminals of the core a first fed-back amplifier with at least one first stage arranged as a folded setup and including first PMOS transistors arranged according to a common-gate setup. Equalizing also includes biasing the first stage based on the CTAT current. The summation of the PTAT and CTAT currents is performed in the feedback stage of the first amplifier.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventors: Jimmy Fort, Thierry Soude
  • Patent number: 9024602
    Abstract: The regulator with low dropout voltage comprises an error amplifier and an output stage comprising an output transistor and a buffer circuit comprising an input connected to the output node of the error amplifier, an output connected to the output transistor, a follower amplifier connected between the input and the output of the buffer circuit. The buffer circuit furthermore comprises a transistor active load connected to the output of the follower amplifier and a negative feedback amplifier arranged in common gate configuration and connected between the output of the follower amplifier and the gate of the transistor of the active load.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: May 5, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Patent number: 8952675
    Abstract: An adjustable bandgap reference voltage includes a first circuit for generating IPTAT, a second circuit for generating ICTAT, and an output module configured to generate the reference voltage. The first circuit includes a first amplifier connected to terminals of a core for equalizing voltages across the terminals, where the first amplifier has a first stage that is biased by the current inversely proportional to absolute temperature and is arranged according to a folded setup with first PMOS transistors arranged according to a common-gate setup. The first circuit also includes a feedback stage with an input connected to the first amplifier output. The feedback stage output is connected to the first stage input and to a terminal of the core. The second circuit includes a follower amplifier connected to a terminal of the core and separated from the first amplifier and the output module is connected to the feedback stage.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Patent number: 8947069
    Abstract: According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Generating the adjustable bandgap reference also includes generating a current inversely proportional to absolute temperature (CTAT), summing the PTAT and the CTAT currents and generating the bandgap reference voltage based on the sum of the currents. Equalizing includes connecting-across the terminals of the core a first fed-back amplifier with at least one first stage arranged as a folded setup and including first PMOS transistors arranged according to a common-gate setup. Equalizing also includes biasing the first stage based on the CTAT current. The summation of the PTAT and CTAT currents is performed in the feedback stage of the first amplifier.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: February 3, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude