Patents by Inventor Thilo Marx
Thilo Marx has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20060022908Abstract: A driving circuit for a display with display elements in rows and/or columns has a shift register, through which tokens are shifted. The shift register's parallel outputs are latched and enable switch cells depending on the tokens. Control signals are supplied to the switch cells which control the output signal in terms of pulse width and/or signal shape. Buffers output the signals to a connected display. Individual or groups of buffers are connected to different supply voltages. The shift register may have more than one input in order to allow for shifting tokens in parallel, e.g. to every second output, using only one clock cycle. Further, inputs are provided for inverting the travelling direction of the tokens, inverting the shape of the signal that is output or switching all outputs to a predetermined state.Type: ApplicationFiled: July 19, 2005Publication date: February 2, 2006Inventors: Thomas Schwanenberger, Heinrich Schemmann, Thilo Marx
-
Patent number: 6928025Abstract: An output circuit (OUT) can be activated via an activation input (AKT), in the activated state starts an output process for data (D) to be read out, in synchronism with the first internal clock (CLKI1), and outputs the data (D) with a specific phase shift (?TOUT) with respect to the first internal clock (CLKI1), in synchronism with the external clock (CLKE), at a data connection (P). A counting unit (CT) starts a counting process for recording the number of successively following first levels of the first internal clock (CLKI1) as soon as a second internal clock (CLKI2), which is synchronized to the external clock (CLKE), for the first time assumes a first level while an output control signal (PAR) is at first level. It activates the output circuit (OUT) as soon as the number of successively following first levels of the first internal clock (CLKI1) has reached a predetermined value.Type: GrantFiled: July 24, 2000Date of Patent: August 9, 2005Assignee: Infineon Technologies AGInventors: Thomas Hein, Thilo Marx, Patrick Heyne, Torsten Partsch
-
Patent number: 6842260Abstract: The imaging system provides assistance during the positioning of a measuring tip as it is placed onto a contact region of a microchip, in order to measure an on-chip signal. The contact region is imaged in a magnified fashion. An insertion device is provided that is suitable for providing a display of the on-chip signal in the imaging plane.Type: GrantFiled: May 28, 2002Date of Patent: January 11, 2005Assignee: Infineon Technologies AGInventors: Stefan Dietrich, Manfred Dobler, Thilo Marx, Peter Mayer
-
Patent number: 6784650Abstract: A switching network with trimmable resistors lies in a control loop of a voltage generator that can be switched off from the supply voltage by a logic device. The logic device and also the switching network are driven by the same signals. The circuit configuration can be used for trimming or switching off the output voltage generated by the voltage generator during the functional test. As many settings as possible for the output voltage can be tested by a small number of control signals.Type: GrantFiled: May 14, 2003Date of Patent: August 31, 2004Assignee: Infienon Technologies AGInventors: Thomas Hein, Patrick Heyne, Thilo Marx, Torsten Partsch
-
Patent number: 6670802Abstract: Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.Type: GrantFiled: October 22, 2001Date of Patent: December 30, 2003Assignee: Infineon Technologies AGInventors: Stefan Dietrich, Patrick Heyne, Thilo Marx, Sabine Kieser, Michael Sommer, Thomas Hein, Michael Markert, Torsten Partsch, Peter Schroegmeier, Christian Weis
-
Patent number: 6661265Abstract: A delay locked loop has a delay unit with a delay time that can be controlled in a manner dependent on a control signal. In order to generate complementary delayed clock signals, provision is made of switching elements, which tap off the clock signal to be delayed along the series circuit of delay elements. Each of the delay elements has a series circuit of two inverters. One of the delayed clock signals is tapped off in each case at the output of the second of the inverters of the delay elements, and the complementary output signal from the delayed output signals is tapped off at the first of the inverters. What is thus made possible is that, disregarding the frequency of the clock signal to be delayed and the length of the delay time, the complementary delayed clock signals always have the same phase angle with respect to one another.Type: GrantFiled: June 24, 2002Date of Patent: December 9, 2003Assignee: Infineon Technologies AGInventors: Torsten Partsch, Thilo Marx, Patrick Heyne, Thomas Hein
-
Patent number: 6657422Abstract: A current mirror circuit has an input path, which has a current source and, connected in series therewith, a first transistor circuit with at least two transistors, wherein one of the transistors can be connected in parallel with the other of the transistors. In an output path, which has a second transistor circuit with at least two transistors, one of the transistors can be connected in parallel with the other of the transistors. The control terminals of the transistors of the first and second transistor circuits can be connected to the input path. As a result, the current mirror circuit can be changed over between two operating modes with a different current requirement with comparatively short changeover times.Type: GrantFiled: December 27, 2001Date of Patent: December 2, 2003Assignee: Infineon Technologies AGInventors: Patrick Heyne, Thilo Marx, Thomas Hein, Torsten Partsch
-
Publication number: 20030205992Abstract: A switching network with trimmable resistors lies in a control loop of a voltage generator that can be switched off from the supply voltage by a logic device. The logic device and also the switching network are driven by the same signals. The circuit configuration can be used for trimming or switching off the output voltage generated by the voltage generator during the functional test. As many settings as possible for the output voltage can be tested by a small number of control signals.Type: ApplicationFiled: May 14, 2003Publication date: November 6, 2003Inventors: Thomas Hein, Patrick Heyne, Thilo Marx, Torsten Partsch
-
Patent number: 6542389Abstract: The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.Type: GrantFiled: October 19, 2001Date of Patent: April 1, 2003Assignee: Infineon Technology AGInventors: Stefan Dietrich, Patrick Heyne, Thilo Marx, Sabine Kieser, Michael Sommer, Thomas Hein, Michael Markert, Torsten Partsch, Peter Schrögmeier, Christian Weis
-
Patent number: 6532188Abstract: An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.Type: GrantFiled: October 29, 2001Date of Patent: March 11, 2003Assignee: Infineon Technologies AGInventors: Stefan Dietrich, Thomas Hein, Patrick Heyne, Thilo Marx, Torsten Partsch, Sabine Kieser, Peter Schroegmeier, Michael Sommer, Christian Weis
-
Publication number: 20030012322Abstract: A delay locked loop includes a delay unit with a controllable delay time. Switching elements are provided in order to tap off output signals from the delay elements of the delay unit. Two nodes connected to the switching elements are connected to a multiplexer configuration in order to activate in each case two of the switching elements that are connected to delay elements connected directly in succession. A phase interpolator generates an intermediate phase from the signals provided.Type: ApplicationFiled: June 24, 2002Publication date: January 16, 2003Inventors: Torsten Partsch, Thomas Hein, Thilo Marx, Patrick Heyne
-
Publication number: 20030002354Abstract: The present invention provides a device for driving a memory cell (601) of a memory module which can be operated with an external voltage (VEXT) and an operating frequency (fCLK), the memory cell (601) having a capacitance (600) for storing charges and a transistor (602) for reading charges from the capacitance (600) and for writing charges to the capacitance (600), which transistor can be controlled with a control voltage (VPP), having a charge store (614) for supplying a control voltage (VPP) which is greater than the external voltage (VEXT), the charge store (614) being able to be charged by the external voltage (VEXT), and the charging of the charge store (614) being able to be controlled by a charging control frequency (fCC) derived from the operating frequency (fCLK) of the memory module.Type: ApplicationFiled: June 26, 2002Publication date: January 2, 2003Inventors: Peter Schroegmeier, Thilo Marx, Manfred Dobler
-
Publication number: 20030001636Abstract: A delay locked loop has a delay unit with a delay time that can be controlled in a manner dependent on a control signal. In order to generate complementary delayed clock signals, provision is made of switching elements, which tap off the clock signal to be delayed along the series circuit of delay elements. Each of the delay elements has a series circuit of two inverters. One of the delayed clock signals is tapped off in each case at the output of the second of the inverters of the delay elements, and the complementary output signal from the delayed output signals is tapped off at the first of the inverters. What is thus made possible is that, disregarding the frequency of the clock signal to be delayed and the length of the delay time, the complementary delayed clock signals always have the same phase angle with respect to one another.Type: ApplicationFiled: June 24, 2002Publication date: January 2, 2003Inventors: Torsten Partsch, Thilo Marx, Patrick Heyne, Thomas Hein
-
Publication number: 20020178392Abstract: An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first signal with the second clock, and second means samples the first signal with a clock phase shifted to the second clock. Means for generating the second signal generates the second signal based on the second clock if it has been determined by at least one means for sampling that the first signal has the predetermined state. Especially for time critical applications, such as a DDR-RAM, a valuable latency saving is provided by the present invention.Type: ApplicationFiled: May 10, 2002Publication date: November 28, 2002Inventors: Thilo Marx, Peter Schrogmeier
-
Publication number: 20020176447Abstract: A Method for initializing an asynchronous latch chain is described, wherein data are taken over through a latch stage at the beginning of the latch chain upon a request signal, the method comprising starting of a clock creation means, like for example a DLL (DLL=delay locket loop), for creating an internal clock on the basis of an external clock, resetting the asynchronous latch chain and applying a start signal to a request signal generation circuit whereupon the creation of a first request signal is enabled on the basis of the internal clock after the clock creation means is settled and after the asynchronous latch chain is reset.Type: ApplicationFiled: April 30, 2002Publication date: November 28, 2002Inventors: Thilo Marx, Peter Schrogmeier
-
Publication number: 20020176095Abstract: The imaging system provides assistance during the positioning of a measuring tip as it is placed onto a contact region of a microchip, in order to measure an on-chip signal. The contact region is imaged in a magnified fashion. An insertion device is provided that is suitable for providing a display of the on-chip signal in the imaging plane.Type: ApplicationFiled: May 28, 2002Publication date: November 28, 2002Inventors: Stefan Dietrich, Manfred Dobler, Thilo Marx, Peter Mayer
-
Patent number: 6480024Abstract: A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.Type: GrantFiled: October 19, 2001Date of Patent: November 12, 2002Assignee: Infineon Technologies AGInventors: Stefan Dietrich, Thomas Hein, Patrick Heyne, Michael Markert, Thilo Marx, Torsten Partsch, Sabine Schöniger Kieser, Peter Schrögmeier, Michael Sommer, Christian Weis
-
Publication number: 20020141279Abstract: An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.Type: ApplicationFiled: October 29, 2001Publication date: October 3, 2002Inventors: Stefan Dietrich, Thomas Hein, Patrick Heyne, Thilo Marx, Torsten Partsch, Sabine Kieser, Peter Schroegmeier, Michael Sommer, Christian Weis
-
Publication number: 20020133750Abstract: Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.Type: ApplicationFiled: October 22, 2001Publication date: September 19, 2002Inventors: Stefan Dietrich, Patrick Heyne, Thilo Marx, Sabine Kieser, Michael Sommer, Thomas Hein, Michael Markert, Torsten Partsch, Peter Schroegmeier, Christian Weis
-
Publication number: 20020093855Abstract: A synchronous semiconductor memory containing dynamic memory cells has a delay locked loop in order to synchronize a clock signal which actuates data output drivers with an externally supplied clock signal. An updating of the delay locked loop is suppressed during a Read state of the semiconductor memory. An appropriate control signal is produced by a state machine and is supplied to the delay locked loop. The synchronization of the data output with the supplied clock signal can be achieved in a precise manner and requires only simple circuitry.Type: ApplicationFiled: January 15, 2002Publication date: July 18, 2002Inventors: Patrick Heyne, Thomas Hein, Torsten Partsch, Thilo Marx