Abstract: A current mirror circuit has an input path, which has a current source and, connected in series therewith, a first transistor circuit with at least two transistors, wherein one of the transistors can be connected in parallel with the other of the transistors. In an output path, which has a second transistor circuit with at least two transistors, one of the transistors can be connected in parallel with the other of the transistors. The control terminals of the transistors of the first and second transistor circuits can be connected to the input path. As a result, the current mirror circuit can be changed over between two operating modes with a different current requirement with comparatively short changeover times.

Abstract: A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

Abstract: The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.

Abstract: A memory chip with a short data access time limits the propagation time of a bit on local data line strips which are far away from output amplifiers by centering switches with respect to a center of the cell array strips, wherein the switches are junction points between local data lines and main data lines.

Abstract: DDR SDRAM memory chips require a highly precise output clock signal in order to pass the stored data onto a data highway at the correct instant. This signal is generated by a symmetrical circuit configuration that, by virtue of the integration of a multiplexer in a clock ratio compensator, additionally generates the output clock signal in a minimal time.

Abstract: A phase regulator is connected, on the input side, to the output of a phase comparator and generates a control signal in a manner dependent on the phase difference ascertained by said comparator. Updating of the control signal fed to a control input of a first delay unit is triggered by an edge of the first output clock signal occurring at the clock output of the first delay unit.

Abstract: A memory chip with a short data access time limits the propagation time of a bit on local data line strips which are far away from output amplifiers by centering switches with respect to a center of the cell array strips, wherein the switches are junction points between local data lines and main data lines.

Abstract: DDR SDRAM memory chips require a highly precise output clock signal in order to pass the stored data onto a data highway at the correct instant. This signal is generated by a symmetrical circuit configuration that, by virtue of the integration of a multiplexer in a clock ratio compensator, additionally generates the output clock signal in a minimal time.

Abstract: A voltage generator configuration includes a voltage generator which generates a second voltage from a first voltage using a reference voltage and which can be deactivated by using a deactivation signal. The voltage generator configuration is distinguished in that the deactivation signal is fed to the voltage generator over a line through which the reference voltage is also fed to the voltage generator.

Abstract: The integrated circuit generates an output clock signal with a phase shift relative to a first clock signal. The currents IE=I1 and IL=I2 can be weighted differently by means of control signals. A different phase shift of the output clock signal results depending on the weighting.

Abstract: Data items D1, D2 read from memory cells MC are simultaneously buffer-stored in memory stages Si of a FIFO memory MEM and are read out again simultaneously from said FIFO memory at a later point in time. Output units OC1, OC2 serve for outputting, at a data output P, the first data D1 synchronously with positive edges of an external clock signal CLK and the second data D2 synchronously with negative edges of the external clock signal CLK.

Abstract: The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.

Abstract: In a semiconductor memory, bit lines are disposed in such a way that in each case two inverted and two non-inverted bit lines lie next to one another. Adjacent switching transistors for connecting the bit lines to an inverted or a non-inverted collective line are connected to the corresponding collective line by a common contact. An advantage in terms of area is afforded by the fact that the two switching transistors have a common doping region.

Abstract: The integrated memory has a data line pair, which is connected to a bit line pair via at least one differential amplifier. In addition, it has a control unit for setting first potential states on the data line pair which correspond to the differential signals of data to be written to the memory cells, and for setting at least one second potential state on the data line pair which does not correspond to any datum to be written to the memory cells. Furthermore, it has a detector unit having two inputs connected to the data line pair. The detector unit initiates a specific control function when the second potential state of the data line pair occurs.