Patents by Inventor Thilo Schaffroth
Thilo Schaffroth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8914589Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.Type: GrantFiled: September 22, 2008Date of Patent: December 16, 2014Assignee: Infineon Technologies AGInventors: Peter Gregorius, Thomas Hein, Martin Maier, Hermann Ruckerbauer, Thilo Schaffroth, Ralf Schedel, Wolfgang Spirkl, Johannes Stecker
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Patent number: 8495310Abstract: A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.Type: GrantFiled: September 22, 2008Date of Patent: July 23, 2013Assignee: Qimonda AGInventors: Peter Gregorius, Thomas Hein, Martin Maier, Hermann Ruckerbauer, Thilo Schaffroth, Ralf Schedel, Wolfgang Spirkl, Johannes Stecker
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Patent number: 7728648Abstract: A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode.Type: GrantFiled: February 15, 2008Date of Patent: June 1, 2010Assignee: Qimonda AGInventors: Alessandro Minzoni, Thilo Schaffroth
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Publication number: 20100077139Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.Type: ApplicationFiled: September 22, 2008Publication date: March 25, 2010Inventors: PETER GREGORIUS, THOMAS HEIN, MARTIN MAIER, HERMANN RUCKERBAUER, THILO SCHAFFROTH, RALF SCHEDEL, WOLFGANG SPIRKL, JOHANNES STECKER
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Publication number: 20100077157Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, the memory device may be a package comprising a plurality of stacked memory dies.Type: ApplicationFiled: September 22, 2008Publication date: March 25, 2010Inventors: Peter Gregorius, Thomas Hein, Martin Maier, Hermann Ruckerbauer, Thilo Schaffroth, Ralf Schedel, Wolfgang Spirkl, Johannes Stecker
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Publication number: 20080197915Abstract: A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode.Type: ApplicationFiled: February 15, 2008Publication date: August 21, 2008Applicant: QIMONDA AGInventors: Alessandro Minzoni, Thilo Schaffroth
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Publication number: 20070247944Abstract: An integrated semiconductor memory with refreshing of memory cells includes a temperature sensor to detect a chip temperature of the integrated semiconductor memory, a connection to apply a command signal, a frequency generation unit to generate a frequency signal, and a memory cell to store a data item, the stored data item being refreshed at the frequency of the frequency signal. The frequency generation unit generates the frequency signal at a first frequency on the basis of a chip temperature detected by the temperature sensor when a first state of the command signal is applied and the frequency generation unit generates the frequency signal at a second frequency, which is changed in comparison with the first frequency, at the same chip temperature when a second state of the command signal is applied.Type: ApplicationFiled: April 24, 2007Publication date: October 25, 2007Applicant: QIMONDA AGInventors: Frank Fischer, Manfred Proll, Thilo Schaffroth, Stephan Schroder
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Patent number: 7165198Abstract: A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of which has an input and an output. The sequence includes at least first and second test-mode storage devices located at corresponding first and second locations on the integrated circuit and configured to store first and second test modes. The first test-mode storage device is configured to perform a shift operation by providing the first test-mode at its output. The second test-mode storage device has its input connected to the output of the first test-mode storage device. This second device is configured to perform the shift operation by receiving, at its input, the first test mode and providing, at its output, the second test-mode.Type: GrantFiled: July 16, 2002Date of Patent: January 16, 2007Assignee: Infineon Technologies AGInventors: Robert Kaiser, Thilo Schaffroth
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Patent number: 6754110Abstract: A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.Type: GrantFiled: July 8, 2002Date of Patent: June 22, 2004Assignee: Infineon Technologies AGInventors: Peter Beer, Thilo Schaffroth
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Patent number: 6734695Abstract: A method and a semiconductor component are described in which an internal voltage to be measured is divided via a matched voltage divider, and is passed to a selected connecting pin. Since there are normally no unused connecting pins, in, for example, present-day large scale integrated components, the connected module is disconnected from a selected connecting pin for a specific time period, and the divided measurement voltage is passed to the connecting pin. This is done by use of a controller, which operates appropriate switches. This method is preferably used for memory components such as DRAM, SRAM etc.Type: GrantFiled: March 6, 2002Date of Patent: May 11, 2004Assignee: Infineon Technologies AGInventors: Thilo Schaffroth, Ralf Schneider
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Patent number: 6675322Abstract: A self-test device serves for carrying out a self-test of an integrated circuit. An output of the self-test device is connected to a contact-making point of the circuit, which serves for external contact-making and which is connected to an input of a circuit unit of the integrated circuit to be tested. The self-test device feeds a test signal through the contact-making point to the circuit unit.Type: GrantFiled: July 19, 1999Date of Patent: January 6, 2004Assignee: Siemens AktiengesellschaftInventors: Thilo Schaffroth, Florian Schamberger, Helmut Schneider
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Patent number: 6628156Abstract: An integrated circuit has a timing circuit with a power source and a capacitor. The timing circuit outputs an output signal whose time can be adjusted and which has a switching time delayed with respect to a reference time. A control signal output by a drive circuit is connected to the timing circuit for adjustment of the output signal with regard to the switching time. The output signal from the timing circuit is connected to the drive circuit for assessment of the output signal with regard to the switching time. The operation of the timing circuit can thus be adjusted independently of process fluctuations during the production of the integrated circuit.Type: GrantFiled: July 2, 2001Date of Patent: September 30, 2003Assignee: Infineon Technologies AGInventors: Robert Kaiser, Thilo Schaffroth
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Patent number: 6603699Abstract: The invention relates to a configuration for fuse initialization, in which the fuse initialization signals bFPUP, FPUN are carried on a total of two lines to the individual fuse banks, and are sent back with a time delay.Type: GrantFiled: October 16, 2001Date of Patent: August 5, 2003Assignee: Infineon Technologies AGInventors: Helmut Fischer, Thilo Schaffroth
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Publication number: 20030028824Abstract: A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of which has an input and an output. The sequence includes at least first and second test-mode storage devices located at corresponding first and second locations on the integrated circuit and configured to store first and second test modes. The first test-mode storage device is configured to perform a shift operation by providing the first test-mode at its output. The second test-mode storage device has its input connected to the output of the first test-mode storage device. This second device is configured to perform the shift operation by receiving, at its input, the first test mode and providing, at its output, the second test-mode.Type: ApplicationFiled: July 16, 2002Publication date: February 6, 2003Inventors: Robert Kaiser, Thilo Schaffroth
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Patent number: 6507528Abstract: A circuit configuration for generating sense amplifier control signals for a DRAM. The circuit configuration includes, in addition to thin oxide transistors that are supplied with a normal standard supply voltage, thick oxide transistors to which an increased supply voltage is applied to compensate for voltage and technological fluctuations.Type: GrantFiled: October 18, 2001Date of Patent: January 14, 2003Assignee: Infineon Technologies AGInventors: Ioannis Chrissostomidis, Thilo Schaffroth, Helmut Fischer
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Publication number: 20030007391Abstract: A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.Type: ApplicationFiled: July 8, 2002Publication date: January 9, 2003Inventors: Peter Beer, Thilo Schaffroth
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Patent number: 6449206Abstract: In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.Type: GrantFiled: May 29, 2001Date of Patent: September 10, 2002Assignee: Infineon Technologies AGInventors: Robert Kaiser, Jürgen Lindolf, Thilo Schaffroth, Florian Schamberger, Helmut Schneider
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Publication number: 20020075741Abstract: A circuit configuration for generating sense amplifier control signals for a DRAM. The circuit configuration includes, in addition to thin oxide transistors that are supplied with a normal standard supply voltage, thick oxide transistors to which an increased supply voltage is applied to compensate for voltage and technological fluctuations.Type: ApplicationFiled: October 18, 2001Publication date: June 20, 2002Inventors: Ioannis Chrissostomidis, Thilo Schaffroth, Helmut Fischer
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Publication number: 20020044492Abstract: The invention relates to a configuration for fuse initialization, in which the fuse initialization signals bFPUP, FPUN are carried on a total of two lines to the individual fuse banks, and are sent back with a time delay.Type: ApplicationFiled: October 16, 2001Publication date: April 18, 2002Inventors: Helmut Fischer, Thilo Schaffroth
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Patent number: 6370069Abstract: A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.Type: GrantFiled: May 29, 2001Date of Patent: April 9, 2002Assignee: Infineon Technologies AGInventors: Eckhard Brass, Thilo Schaffroth, Joachim Schnabel, Helmut Schneider