Abstract: An integrated circuit is described which has a timing circuit with a power source and a capacitance. The timing circuit outputs an output signal whose time can be adjusted and which has a switching time delayed with respect to a reference time. A control signal output by a drive circuit is connected to the timing circuit for adjustment of the output signal with regard to the switching time. The output signal from the timing circuit is connected to the drive circuit for assessment of the output signal with regard to the switching time. The operation of the timing circuit can thus be adjusted independently of process fluctuations during the production of the integrated circuit.

Abstract: In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.

Abstract: A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.

Abstract: A method of testing leakage current at a contact-making point in an integrated circuit includes applying a test potential to the contact-making point through an output of an application device. The output of the application device is connected to a high impedance or is isolated from the contact-making point. The potential at the contact-making point is determined as a measure of the leakage current being produced.

Abstract: An adjustable delay circuit for digital signals includes a series circuit which is disposed between two supply potentials and has at least a first transistor of a first conduction type and second and third transistors of a second conduction type. Control connections of the first and second transistors are connected to a signal input of the delay circuit. One connection of the first transistor, which is remote from the first supply potential, is connected to a signal output. A fourth transistor of the second conduction type is connected in parallel with the third transistor. A first control input is connected to a control connection of the third transistor and a second control input is connected to a control connection of the fourth transistor. The control inputs are used to adjust the delay time of the delay circuit.

Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.