Patents by Inventor Thilo Scheiper

Thilo Scheiper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357883
    Abstract: A power semiconductor device includes an active region having a total volume with a central volume forming at least 20% of the total volume, a peripheral volume forming at least 20% of the total volume and surrounding the central volume, and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The peripheral volume has a constant lateral distance from an edge termination region. A first doped semiconductor region is electrically connected with a first load terminal at a semiconductor body frontside. A second doped semiconductor region is electrically connected with a second load terminal at a semiconductor body backside. The first and/or second doped semiconductor region has: a central portion extending into the central volume and having a central average dopant dose; and a peripheral portion extending into the peripheral volume and having a peripheral average dopant dose.
    Type: Application
    Filed: May 6, 2020
    Publication date: November 12, 2020
    Inventors: Manfred Pfaffenlehner, Josef-Georg Bauer, Frank Dieter Pfirsch, Thilo Scheiper, Konrad Schraml
  • Patent number: 9490344
    Abstract: Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
  • Patent number: 9490361
    Abstract: Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle ? preferably about ?90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Stefan Flachowsky, Thilo Scheiper
  • Patent number: 9490189
    Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 9425052
    Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Jan Hoentschel, Steven Langdon
  • Patent number: 9184095
    Abstract: In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Sven Beyer, Uwe Griebenow, Jan Hoentschel, Andy Wei
  • Publication number: 20150228490
    Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.
    Type: Application
    Filed: April 28, 2015
    Publication date: August 13, 2015
    Inventors: Thilo Scheiper, Jan Hoentschel, Steven Langdon
  • Patent number: 9082662
    Abstract: When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: July 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Stefan Flachowsky
  • Patent number: 9054207
    Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Sven Beyer, Uwe Griebenow, Jan Hoentschel
  • Patent number: 9048336
    Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 2, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Jan Hoentschel, Steven Langdon
  • Patent number: 9040403
    Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: May 26, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Thilo Scheiper, Stefan Flachowsky, Andy Wei
  • Patent number: 9023696
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: May 5, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Marco Lepper, Thilo Scheiper
  • Patent number: 8987104
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Sven Beyer, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8975704
    Abstract: A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jan Hoentschel, Shiang Yang Ong, Stefan Flachowsky, Thilo Scheiper
  • Publication number: 20150054072
    Abstract: A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
    Type: Application
    Filed: October 6, 2014
    Publication date: February 26, 2015
    Inventors: Jan HOENTSCHEL, Shiang Yang ONG, Stefan FLACHOWSKY, Thilo SCHEIPER
  • Patent number: 8936977
    Abstract: A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: January 20, 2015
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Jan Hoentschel, Shiang Yang Ong, Stefan Flachowsky, Thilo Scheiper
  • Patent number: 8916433
    Abstract: When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Baars, Sven Beyer
  • Patent number: 8872285
    Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: October 28, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Carsten Grass, Richard Carter, Martin Trentzsch
  • Patent number: 8871586
    Abstract: In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: October 28, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Jan Hoentschel, Markus Lenski, Rolf Stephan
  • Publication number: 20140246735
    Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Thilo Scheiper, Carsten Grass, Richard Carter, Martin Trentzsch