Abstract: The present business method transparently embeds advertisements into client browser displays at the edge of the Internet. A closed system of locally owned businesses makes up a network of publication points. The business method uses a simple single page “dashboard” interface to select and publish ad campaigns directly into one or more premises helping to qualify and quantify publication points and advertising subscription purchases. The dashboards display has controls to dynamically update campaign publications and display pricing results. In addition, the method builds and displays custom groups based on location, business types, and customer demographics. Thus, custom grouping options as selected by dashboard users. Subscription pricing is by ad size, type, location, subscription period and discount codes. The dashboard may include additional statistics such as subscription renewal dates and ad convergence information.

Abstract: A network device, also referred to as the Compression Enhanced Network Processor (CENP), with embedded parallel (or fast serial) compression and/or decompression capability. The network device may be a network processor based multi-ported switch, bridge, router, hub, or other device. The CENP may provide improved data density, efficiency and bandwidth for each port of a multi-port network switch. In one embodiment, the CENP may comprise a network processor core, a memory management unit, a memory buffer (e.g., an SRAM memory buffer), and a system memory. The CENP may comprise a compression and decompression engine. In one embodiment, the memory management unit comprises the compression and decompression engine, and thus may be referred to as a Compression Enhanced Memory Controller Unit (CEMCU).

Abstract: An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. The IMC preferably uses a lossless data compression and decompression scheme. Data transfers to and from the integrated memory controller of the present invention can thus be in either two formats, these being compressed or normal (non-compressed). The IMC also preferably includes microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data from system I/O peripherals such as the hard drive, floppy drive, or local area network (LAN) are decompressed in the IMC and stored into system memory or saved in the system memory in compressed format.

Abstract: As prior art systems fail to produce end-to-end transport and routing mechanisms capable of secure, accurate, and timely delivery of real-time media, the present invention prescribes the method and process to facilitate server-less, IP based sessions across all of public and private network infrastructure without regard for network hardware or carrier makeup. The method and process claimed herein defines the application of well known standards in a unique fashion so as to facilitate transportation of TCP and UDP packets associated with a real-time multicast session in a secure manner while achieving unencumbered access through firewalls and across multiple carrier, public networks through IPSec based virtual networking.

Abstract: As prior art systems fail to produce end-to-end transport and routing mechanisms capable of secure, accurate, and timely delivery of real-time media, the present invention prescribes the method and process to facilitate server-less, IP based sessions across all of public and private network infrastructure without regard for network hardware or carrier makeup. The method and process claimed herein defines the application of well known standards in a unique fashion so as to facilitate transportation of TCP and UDP packets associated with a real-time multicast session in a secure manner while achieving unencumbered access through firewalls and across multiple carrier, public networks through IPSec based virtual networking.

Abstract: An integrated memory controller (IMC) including MemoryF/X Technology which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably selectively uses a combination of lossless, lossy, and no compression modes. Data transfers to and from the integrated memory controller of the present invention can thus be in a plurality of formats, these being compressed or normal (non-compressed), compressed lossy or lossless, or compressed with a combination of lossy and lossless. The invention also indicates preferred methods for specific compression and decompression of particular data formats such as digital video, 3D textures and image data using a combination of novel lossy and lossless compression algorithms in block or span addressable formats.

Abstract: A parallel decompression system and method that decompresses input compressed data in one or more decompression cycles, with a plurality of tokens typically being decompressed in each cycle in parallel. A parallel decompression engine may include an input for receiving compressed data, a history window, and a plurality of decoders for examining and decoding a plurality of tokens from the compressed data in parallel in a series of decompression cycles. Several devices are described that may include the parallel decompression engine, including intelligent devices, network devices, adapters and other network connection devices, consumer devices, set-top boxes, digital-to-analog and analog-to-digital converters, digital data recording, reading and storage devices, optical data recording, reading and storage devices, solid state storage devices, processors, bus bridges, memory modules, and cache controllers.

Abstract: A system and method for managing a functional unit in a system using a data movement engine. An exemplary system may comprise a CPU coupled to a memory controller. The memory controller may include or couple to a data movement engine (DME). The memory controller may in turn couple to a system memory or other device which includes at least one functional unit. The DME may operate to transfer data to/from the system memory and/or the functional unit, as described herein. In one embodiment, the DME may also include multiple DME channels or multiple DME contexts. The DME may operate to direct the functional unit to perform operations on data in the system memory. For example, the DME may read source data from the system memory, the DME may then write the source data to the functional unit, the functional unit may operate on the data to produce modified data, the DME may then read the modified data from the functional unit, and the DME may then write the modified data to a destination in the system memory.

Abstract: A method and system for allowing a processor or I/O master to address more system memory than physically exists are described. A Compressed Memory Management Unit (CMMU) may keep least recently used pages compressed, and most recently and/or frequently used pages uncompressed in physical memory. The CMMU translates system addresses into physical addresses, and may manage the compression and/or decompression of data at the physical addresses as required. The CMMU may provide data to be compressed or decompressed to a compression/decompression engine. In some embodiments, the data to be compressed or decompressed may be provided to a plurality of compression/decompression engines that may be configured to operate in parallel. The CMMU may pass the resulting physical address to the system memory controller to access the physical memory. A CMMU may be integrated in a processor, a system memory controller or elsewhere within the system.

Abstract: A method and system for identifying and configuring device-enhanced memory modules at system startup is described. A driver is described that performs a wakeup procedure at startup to identify installed device-enhanced memory modules, detect memory implementations such as interleaving and striping on memory modules, detect error detection and correction (ECC) implementations, and to configure the identified device-enhanced memory modules to use the detected implementations. The method may include several phases including, but not limited to, a start block phase, an ECC configuration phase, an ECC check phase, an interleave detect and configuration phase, a buffer check phase, and a final configuration phase. One or more of the phases may be performed at system startup and/or during normal system operation. Methods for shutting down and providing a sleep mode for device-enhanced memory modules are also described.

Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of data compression engines each implementing a different data compression algorithm. A codec system may be designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. Uncompressed data may be compressed using a plurality of compression engines in parallel, with each engine compressing the data using a different lossless data compression algorithm. At least one of the data compression engines may implement a parallel lossless data compression algorithm designed to process stream data at more than a single byte or symbol at one time. The plurality of different versions of compressed data generated by the different compression algorithms may be examined to determine an optimal version of the compressed data according to one or more predetermined criteria. A codec system may be integrated in a processor, a system memory controller or elsewhere within a system.

Abstract: An memory module including parallel data compression and decompression engines for improved performance. The memory module includes MemoryF/X Technology. To improve latency and reduce performance degradations normally associated with compression and decompression techniques, the MemoryF/X Technology encompasses multiple novel techniques such as: 1) parallel lossless compression/decompression; 2) selectable compression modes such as lossless, lossy or no compression; 3) priority compression mode; 4) data cache techniques; 5) variable compression block sizes; 6) compression reordering; and 7) unique address translation, attribute, and address caches. The parallel compression and decompression algorithm allows high-speed parallel compression and high-speed parallel decompression operation. The memory module-integrated data compression and decompression capabilities remove system bottlenecks and increase performance.

Abstract: A parallel decompression system and method which decompresses input compressed data in one or more decompression cycles, with a plurality of tokens typically being decompressed in each cycle in parallel. A parallel decompression engine may include an input for receiving compressed data, a history window, and a plurality of decoders for examining and decoding a plurality of tokens from the compressed data in parallel in a series of decompression cycles. A token may represent one or more compressed symbols or one uncompressed symbol. The parallel decompression engine may also include preliminary select generation logic for generating a plurality of preliminary selects in parallel. A preliminary select may point to an uncompressed symbol in the history window, an uncompressed symbol from a token in the current decompression cycle, or a symbol being decompressed in the current decompression cycle.

Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of parallel data compression and/or parallel data decompression engines designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. The plurality of compression/decompression engines may each implement a parallel lossless data compression/decompression algorithm. The codec system may split incoming uncompressed or compressed data up among the plurality of compression/decompression engines. Each of the plurality of compression/decompression engines may compress or decompress a particular part of the data. The codec system may then merge the portions of compressed or uncompressed data output from the plurality of compression/decompression engines. The codec system may implement a method for performing parallel data compression and/or decompression designed to process stream data at more than a single byte or symbol at one time.

Abstract: A method which allows standard telephone users to audio conference with video conferencing participants over IP networks in a private secure environment. A dial-out is performed from one or more conference client terminals bridging audio between the Internet and the PSTN networks. The process uses a mixed mode hybrid network architecture for call set-up, initialization and teardown including the method to mix audio at the desktop terminal instead of in a general purpose server as in the prior art. The method conferences video and audio between multiple clients and include audio from a standard telephone network within the conference. A virtual private network connects all of the IP clients together including the voice over IP server used to transcode the proprietary audio into the H.323 standard for transport into the telephony network.

Abstract: As prior art systems fail to produce end-to-end transport and routing mechanisms capable of secure, accurate, and timely delivery of real-time media, the present invention prescribes the method and process to facilitate server-less, IP based sessions across all of public and private network infrastructure without regard for network hardware or carrier makeup. The method and process claimed herein defines the application of well known standards in a unique fashion so as to facilitate transportation of TCP and UDP packets associated with a real-time multicast session in a secure manner while achieving unencumbered access through firewalls and across multiple carrier, public networks through IPSec based virtual networking.

Abstract: A method and process used to improve the quality of multi participant video conferencing over Internet protocol which uses a unique feedback control loop to dynamically adjust for transport discrepancies commonly found in standard IP networks. The bit-rate of compressed video is adjusted by the limitation of data transport thru the network. Decimation of compressed objects represented by spatial and temporal sub bands of information during times of long latency or limited bandwidth are used to reduce the transmit bit-rate. Wavelet transforms are used for the derivation of spatial and temporal sub-band. Linear summation of decompressed sub-bands during the Inverse wavelet transform allows a quality of image based on the number of object or frame sub-bands received per given frame time. Error signals are developed based on the expected sub-band transport and the actual received number of sub-bands.

Abstract: A method and process for improving the quality of multi participant video conferencing over Internet Protocol. The method uses a unique grayscale area map that represents objects in 3-D space to determine area boundaries and object priority for culling prior to transport. The method uses an objects depth map to determine the highest energy magnitude for motion estimation and compensation. By controlling the flow rate of objects over the temporal domain and the re-creation of object based predictive frames, a constant bit-rate scalable video compression algorithm has been shown. Spatial and temporal hierarchical significance trees are used to build maps of significant energy on a per-object basis. Thus, the bit-rate of compressed video is dynamically adjusted by the limitation of data transport through the network.

Abstract: A graphics controller which performs display list-based video refresh operations that enable objects with independent frame rates to be efficiently assembled is disclosed. The graphics controller maintains a virtual display refresh list (VDRL) comprising a plurality of pointers to scan line segments in memory. The graphics controller also creates, maintains, and deletes draw display lists (DDLs) that comprise pointers to object display list subroutines (ODLs) that independently draw objects in memory. The ODLs may allocated one or more buffers in memory into which different frames of the objects are drawn. When an ODL has completed executing, the corresponding pointer in the DDL may be updated to point to the buffer location in memory that stores the newly completed object frame. The VDRL is maintained independently (and may be doubled-buffered) and is updated using the DDLs.

Abstract: A system and method for managing a functional unit in a system using a data movement engine. An exemplary system may comprise a CPU coupled to a memory controller. The memory controller may include or couple to a data movement engine (DME). The memory controller may in turn couple to a system memory or other device which includes at least one functional unit. The DME may operate to transfer data to/from the system memory and/or the functional unit, as described herein. In one embodiment, the DME may also include multiple DME channels or multiple DME contexts. The DME may operate to direct the functional unit to perform operations on data in the system memory. For example, the DME may read source data from the system memory, the DME may then write the source data to the functional unit, the functional unit may operate on the data to produce modified data, the DME may then read the modified data from the functional unit, and the DME may then write the modified data to a destination in the system memory.