Abstract: An improved method and apparatus for rendering curved surfaces in a graphics system. The appearance of a curved surface is created by varying color shades across an object. The graphics systems represents each primary color with fewer than eight bits. The present invention maintains smooth transaction between color shades despite using fewer than eight bits to represent color. An eight bit color shade value is truncated, with the most significant bits being saved and used as a color value. The least significant bits that are truncated are used to determine which of the adjacent color values to use to render pixels. Thus, if five bits are saved and used to represent a color, the three least significant truncated bits are used to determine the appropriate mix of the closest five bit shades. The three truncated bits are used to select an entry from a ramp table and a control signal from a look-up table selects a bit from the selected ramp table entry.

Abstract: A graphics controller (IMC) which performs pointer-based and/or display list-based video refresh operations that enable screen refresh data to be assembled on a per window basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various buffers in system memory comprising video or graphics display information. The graphics controller manipulates respective object information workspace memory areas corresponding to each object or window, wherein the workspace areas specify data types, color depths, 3D depth values, alpha blending information, screen position, etc. for the respective window or object on the screen. Each workspace area also includes static and dynamic pointers which point to the location in system memory where the pixel data for the respective window or object is stored.

Abstract: A method and apparatus that adjusts certain graphics processing procedures based on a selectable speed/quality (S/Q) adjustment gauge. The S/Q adjustment can be tuned within a predetermined range (e.g., 0 to 255) where on one side, speed is represented over image quality while on the other side, image quality is represented over speed. Settings between the ends give proportional representation for speed and quality. A first graphics process determines whether linear or perspective texture mapping processes are to be used on the selected polygon based on: 1) the size of the polygon measured against a predetermined size threshold; and 2) the relative perspective of the polygon measured against a perspective threshold. The S/Q setting alters these thresholds to alter the operation of the first graphics procedure. A second graphics process splits a selected polygon graphics primitive based on the relative perspective of the polygon compared to a predetermined perspective threshold.

Abstract: A graphics system including a frame buffer having two or more buffers, a graphics processor and system memory. The graphics processor includes rendering logic, display logic and a buffer switch memory that stores an address. The display logic reads the address from the buffer switch memory and retrieves rendered data for display from one of the buffers. The rendering logic retrieves a next display list from the system memory after a continue indication is provided, renders the retrieved display list into another buffer, writes an address corresponding to the other buffer into the buffer switch memory and clears the continue indication. The continue indication may be a separate bit or a continue flag provided within each display list. The rendering logic sequences through the plurality of buffers in this manner to render a plurality of display lists. If only two buffers are provided, then the buffer switch memory includes an arm bit and the rendering logic sets the arm bit after rendering each display list.

Abstract: A graphics controller (IMC) which performs pointer-based and/or display list-based video refresh operations that enable screen refresh data to be assembled on a per window basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various buffers in system memory comprising video or graphics display information. The graphics controller manipulates respective object information workspace memory areas corresponding to each object or window, wherein the workspace areas specify data types, color depths, 3D depth values, alpha blending information, screen position, etc. for the respective window or object on the screen. Each workspace area also includes static and dynamic pointers which point to the location in system memory where the pixel data for the respective window or object is stored.

Abstract: A method and apparatus for synchronizing audio and video data streams in a computer system during a multimedia presentation to produce a correctly synchronized presentation. The preferred embodiment of the invention utilizes a nonlinear feedback method for data synchronization. The method of the present invention periodically queries each driver for the current audio and video position (or frame number) and calculates the synchronization error. The synchronization error is used to determine a tempo value adjustment to one of the data stream designed to place the video and audio back in sync. The method then adjusts the audio or video tempo to maintain the audio and video data streams in synchrony. In the preferred embodiment of the invention, the video tempo is changed nonlinearly over time to achieve a match between the video position and the equivalent audio position. The method applies a smoothing function to the determined tempo value to prevent overcompensation.

Abstract: An incremental orthogonal error correction process for 3D graphics for correcting errors or otherwise reducing abrupt changes in the characteristics of adjacent pixels while interpolating a polygon into a pixel grid. Error values are calculated for each desired characteristic to be corrected, where the error values are calculated based on the slope of the main slope and the orthogonal slope of the corresponding characteristic value. Thus, the error values adjust the characteristics of the pixels in the scan line to adjust for the slant of the main slope of the polygon. An interpolator for each corrected characteristic accumulates the error value in the opposite direction as the corresponding orthogonal slope. When the fractional component of the x parameter overflows, the orthogonal slope values are subtracted from the corresponding accumulated error values to thereby reduce the magnitude of the error values.

Abstract: A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user.

Abstract: A device for reducing access time to RAM arrays, especially DRAMs, by including fast access cache rows, e.g., four rows, to store data from accessed rows of the array, where data can then be accessed without precharging, row decoding sensing, and other cycling usually required to access the DRAM. Address registers, comparators, and MRU/LRU register and other cache control logic may be included in the device. The device allows parallel transfer of data between the RAM array and the cache rows. The device may be constructed on a single chip. A system is disclosed which makes use of the cache RAM features in a data processing system to take advantage of the attributes of a cache RAM memory.

Abstract: A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user.

Abstract: A multi-channel video graphics display system is provided which utilizes a single graphics controller and associated graphics processor to supply independent video graphic information to a plurality of independent display terminals.

Abstract: A multiple oscillator switching circuit for a digital processing system that includes a central processing unit having a first internal timing cycle and connected to a plurality of peripheral devices, each peripheral device having an independent internal timing cycle. The central processing unit is further connected to an oscillator switching circuit. The oscillator switching circuit includes several oscillators. Each oscillator has an output consisting of an independent internal frequency. A selected number of these oscillators have independent internal frequencies that correspond to the internal timing of the peripheral devices. These oscillator switching circuits are further connected to the central processing unit and to the output of each of the oscillators for providing a single oscillator output to the central processing unit in response to an output from the central processing unit.