Patents by Inventor Thomas A. Gregg

Thomas A. Gregg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10616115
    Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A single link interface communicatively couples the send component to the receive component. The single link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard K. Errickson, Thomas A. Gregg, Leonard W. Helmer, Jr., Michael P. Lyons, Kulwant M. Pandey, Peter K. Szwed
  • Patent number: 10223283
    Abstract: Embodiments relate to enhancing a refresh PCI translation (RPCIT) instruction to refresh a translation lookaside buffer (TLB). A computer processor determines a request to purge a translation for a single frame of the TLB in response to executing an enhanced RPCIT instruction. The enhanced RPCIT instruction is configured to selectively perform one of a single-frame TLB refresh operation or a range-bounded TLB refresh operation. The computer processor determines an absolute storage frame based on a translation of a PCI virtual address in response to the request to purge a translation for a single frame of the TLB. The computer processor further performs the single-frame TLB refresh operation to purge the translation for the single frame.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Thomas A. Gregg, Dan F. Greiner, Damian L. Osisek
  • Patent number: 10122653
    Abstract: An energy management system for a data center network may include a central computer to establish an energy use policy for the computer data center network. The system may also include computer nodes in the computer data center network to receive a packet which is a query that obtains energy information from the nodes and/or a transmission reservation that provides instructions for the energy use policy to be implemented at the computer nodes. The computer nodes may reallocate data traffic on the computer data center network based on the energy use policy to improve energy consumption of the computer data center network.
    Type: Grant
    Filed: December 8, 2012
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Thomas A. Gregg, Rajaram B. Krishnamurthy, Anuradha Rao
  • Patent number: 9923824
    Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A link interface communicatively couples the send component to the receive component. The link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard K. Errickson, Thomas A. Gregg, Leonard W. Helmer, Jr., Michael P. Lyons, Kulwant M. Pandey, Peter K. Szwed
  • Publication number: 20180074972
    Abstract: Embodiments relate to enhancing a refresh PCI translation (RPCIT) instruction to refresh a translation lookaside buffer (TLB). A computer processor determines a request to purge a translation for a single frame of the TLB in response to executing an enhanced RPCIT instruction. The enhanced RPCIT instruction is configured to selectively perform one of a single-frame TLB refresh operation or a range-bounded TLB refresh operation. The computer processor determines an absolute storage frame based on a translation of a PCI virtual address in response to the request to purge a translation for a single frame of the TLB. The computer processor further performs the single-frame TLB refresh operation to purge the translation for the single frame.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 15, 2018
    Inventors: David F. Craddock, Thomas A. Gregg, Dan F. Greiner, Damian L. Osisek
  • Publication number: 20180054387
    Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A single link interface communicatively couples the send component to the receive component. The single link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.
    Type: Application
    Filed: November 1, 2017
    Publication date: February 22, 2018
    Inventors: Richard K. Errickson, Thomas A. Gregg, Leonard W. Helmer, JR., Michael P. Lyons, Kulwant M. Pandey, Peter K. Szwed
  • Patent number: 9886391
    Abstract: Embodiments relate to enhancing a refresh PCI translation (RPCIT) instruction to refresh a translation lookaside buffer (TLB). A computer processor determines a request to purge a translation for a single frame of the TLB in response to executing an enhanced RPCIT instruction. The enhanced RPCIT instruction is configured to selectively perform one of a single-frame TLB refresh operation or a range-bounded TLB refresh operation. The computer processor determines an absolute storage frame based on a translation of a PCI virtual address in response to the request to purge a translation for a single frame of the TLB. The computer processer further performs the single-frame TLB refresh operation to purge the translation for the single frame.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Thomas A. Gregg, Dan F. Greiner, Damian L. Osisek
  • Patent number: 9886392
    Abstract: A method of enhancing a refresh PCI translation (RPCIT) operation to refresh a translation lookaside buffer (TLB) includes determining, by a computer processor, a request to perform at least one RPCIT instruction for purging at least one translation from the TLB. The method further includes purging, by the computer processor, the at least one translation from the TLB in response to executing the at least one RPCIT instruction. The computer processor selectively performs a synchronization operation prior to completing the at least one RPCIT instruction.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Thomas A. Gregg, Dan F. Greiner, Damian L. Osisek
  • Patent number: 9880942
    Abstract: A method of enhancing a refresh PCI translation (RPCIT) operation to refresh a translation lookaside buffer (TLB) includes determining, by a computer processor, a request to perform at least one RPCIT instruction for purging at least one translation from the TLB. The method further includes purging, by the computer processor, the at least one translation from the TLB in response to executing the at least one RPCIT instruction. The computer processor selectively performs a synchronization operation prior to completing the at least one RPCIT instruction.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Thomas A. Gregg, Dan F. Greiner, Damian L. Osisek
  • Publication number: 20180006947
    Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A link interface communicatively couples the send component to the receive component. The link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.
    Type: Application
    Filed: September 26, 2017
    Publication date: January 4, 2018
    Inventors: Richard K. Errickson, Thomas A. Gregg, Leonard W. Helmer, JR., Michael P. Lyons, Kulwant M. Pandey, Peter K. Szwed
  • Patent number: 9843518
    Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A link interface communicatively couples the send component to the receive component. The link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard K. Errickson, Thomas A. Gregg, Leonard W. Helmer, Jr., Michael P. Lyons, Kulwant M. Pandey, Peter K. Szwed
  • Patent number: 9794178
    Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A link interface communicatively couples the send component to the receive component. The link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard K. Errickson, Thomas A. Gregg, Leonard W. Helmer, Jr., Michael P. Lyons, Kulwant M. Pandey, Peter K. Szwed
  • Publication number: 20170187626
    Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A link interface communicatively couples the send component to the receive component. The link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.
    Type: Application
    Filed: March 14, 2017
    Publication date: June 29, 2017
    Inventors: Richard K. Errickson, Thomas A. Gregg, Leonard W. Helmer, JR., Michael P. Lyons, Kulwant M. Pandey, Peter K. Szwed
  • Patent number: 9626298
    Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais
  • Patent number: 9628388
    Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A link interface communicatively couples the send component to the receive component. The link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard K. Errickson, Thomas A. Gregg, Leonard W. Helmer, Jr., Michael P. Lyons, Kulwant M. Pandey, Peter K. Szwed
  • Patent number: 9621647
    Abstract: Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard K. Errickson, Thomas A. Gregg, Kulwant M. Pandey
  • Patent number: 9571572
    Abstract: Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard K. Errickson, Thomas A. Gregg, Kulwant M. Pandey
  • Patent number: 9547613
    Abstract: Embodiments include a method and computer program product for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router routes requests received over a universal peripheral component interconnect express (PCIe) port from PCIe adapters utilizing different operating modes. An aspect includes a general purpose host computer with one or more PCIe universal ports allowing the computer to connect to a wide range of external peripheral devices, such as a local area networks, storage area networks, printers, scanners, graphics controllers, game systems, and so forth. PCIe is a modern universal port protocol for parallel ports that allows peripherals utilizing different operating modes to connect to a standard PCIe parallel port. The mixed mode request router supports converged PCIe adapters, which support multiple functions utilizing different PCIe modes converged onto the same mixed mode adapter.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
  • Patent number: 9542243
    Abstract: Embodiments are directed to systems and methodologies for allowing a computer program code to efficiently respond to and process events. For events having a multiple stage completion sequence, and wherein several of the events occur within relatively close time proximity to each other, portions of the multiple stages may be coalesced without adding latency, thereby maintaining responsiveness of the computer program. The disclosed coalescing systems and methodologies include state machines and counters that in effect “replace” certain stages of the event sequence when the frequency of events increases.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas A. Gregg, Kulwant M. Pandey
  • Publication number: 20160352819
    Abstract: Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.
    Type: Application
    Filed: August 23, 2016
    Publication date: December 1, 2016
    Inventors: Richard K. Errickson, Thomas A. Gregg, Kulwant M. Pandey