Patents by Inventor Thomas A. Gregg

Thomas A. Gregg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9134911
    Abstract: An instruction is provided that includes an opcode field to identify a store instruction to store in a designated location current values of operational parameters of an adapter function of an adapter; a first field to identify a location, the contents of which include a function handle identifying a handle of the adapter function for which the store instruction is being performed, and an indication of an address space associated with the adapter function identified by the function handle to which the store instruction applies; and a second field to identify the designated location of where a result of the store instruction is to be stored. Execution of the instruction includes obtaining information from a function information block associated with the adapter function; and copying the information from the function information block into the designated location, based on completion of one or more validity checks with one or more predefined results.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: September 15, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Craddock, Mark S. Farrell, Beth A. Glendening, Thomas A. Gregg, Dan F. Greiner, Gustav E. Sittmann, III, Peter K. Szwed
  • Publication number: 20150183810
    Abstract: The invention includes processes for the synthesis of amphetamine, dexamphetamine, methamphetamine, derivatives of these, including their salts, and novel precursors and intermediates obtained thereby, by synthesizing aziridine phosphoramidate compounds in specified solvents at specified temperatures, and then converting to a novel aryl or aryl-alkyl phosphoramidate precursors using an organometallic compound such as a copper salt, where the novel aryl or aryl-alkyl phosphoramidate precursor is then easily converted to the target compounds using known reactions.
    Type: Application
    Filed: July 9, 2014
    Publication date: July 2, 2015
    Applicant: CHEMAPOTHECA, LLC
    Inventors: Harold Meckler, Brian Thomas Gregg, Jie Yang
  • Publication number: 20150183716
    Abstract: The invention includes processes for the synthesis of amphetamine, dexamphetamine, methamphetamine, derivatives of these, including their salts, and novel precursors and intermediates obtained thereby, by synthesizing aziridine phosphoramidate compounds in specified solvents at specified temperatures, and then converting to a novel aryl or aryl-alkyl phosphoramidate precursors using an organometallic compound such as a copper salt, where the novel aryl or aryl-alkyl phosphoramidate precursor is then easily converted to the target compounds using known reactions,
    Type: Application
    Filed: February 25, 2014
    Publication date: July 2, 2015
    Applicant: CHEMAPOTHECA, LLC
    Inventors: Harold Meckler, Brian Thomas Gregg, Jie Yang
  • Patent number: 9031415
    Abstract: An Ethernet adapter system may include a transmitter to insert a payload type identifier sequence in a generic frame procedure header to indicate that a network is a converged enhanced Ethernet network. The transmitter may insert idle sequences in a stream of data frames transmitted along a link. The system may include a receiver to recognize a condition and to force a loss of synchronization condition on the link that will be converted by the receiver into a loss of light condition. The receiver may scan the transmitted stream of data frames for invalid data frames and introduce a code into the stream of data frames whenever an invalid data frame is detected.
    Type: Grant
    Filed: December 8, 2012
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Thomas A. Gregg, Rajaram B. Krishnamurthy
  • Patent number: 9007904
    Abstract: A system to improve a Fiber Channel over Convergence Enhanced Ethernet (FCoCEE) network may include a sender in an FCoCEE network in which data packets having different data link layer structures are transmitted by the sender on a single data link. The system may also include a receiver to receive the data packets at the data link layer and to transmit an ACK and/or NAK in response to a sequence number in the data packets. The system may further include a replay buffer to retransmit the data packets where the replay buffer is sized by the length of the data link, data rate of the data link, the ACK and/or NAK processing time at either the sender and/or the receiver, and/or a threshold time for transmission and/or reception of the data packets.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Thomas A. Gregg, Rajaram B. Krishnamurthy
  • Patent number: 9007905
    Abstract: A system to improve a Fiber Channel over Convergence Enhanced Ethernet (FCoCEE) network may include a sender in an FCoCEE network in which data packets having different data link layer structures are transmitted by the sender on a single data link. The system may also include a receiver to receive the data packets at the data link layer and to transmit an ACK and/or NAK in response to a sequence number in the data packets. The system may further include a replay buffer to retransmit the data packets where the replay buffer is sized by the length of the data link, data rate of the data link, the ACK and/or NAK processing time at either the sender and/or the receiver, and/or a threshold time for transmission and/or reception of the data packets.
    Type: Grant
    Filed: December 8, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Thomas A. Gregg, Rajaram B. Krishnamurthy
  • Patent number: 8934783
    Abstract: An Ethernet adapter system may include a transmitter to insert a payload type identifier sequence in a generic frame procedure header to indicate that a network is a converged enhanced Ethernet network. The transmitter may insert idle sequences in a stream of data frames transmitted along a link. The system may include a receiver to recognize a condition and to force a loss of synchronization condition on the link that will be converted by the receiver into a loss of light condition. The receiver may scan the transmitted stream of data frames for invalid data frames and introduce a code into the stream of data frames whenever an invalid data frame is detected.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Thomas A. Gregg, Rajaram B. Krishnamurthy
  • Patent number: 8918573
    Abstract: Embodiments of the invention relate to optimizing EDRAM refresh rates in a high performance cache architecture. A request is received from a requester to perform an operation on an I/O adapters. It is determined if the request is in a format other than a format supported by an I/O bus and if, the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus and is transmitted to the requester.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, David F. Craddock, Eric N. Lais
  • Patent number: 8776066
    Abstract: Execution of tasks on accelerator units is managed. The managing includes multi-level grouping of tasks into groups based on defined criteria, including start time of tasks and/or deadline of tasks. The task groups and possibly individual tasks are mapped to accelerator units to be executed. During execution, redistribution of a task group and/or an individual task may occur to optimize a defined energy profile.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Rajaram B. Krishnamurthy, Thomas A. Gregg
  • Patent number: 8769180
    Abstract: Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, David F. Craddock, Eric N. Lais
  • Patent number: 8762125
    Abstract: A computer program product, apparatus and method for emulating channels in a multi-tasking multi-processor environment, including identifying a plurality of physical channels having an associated physical channel identifier for each of the plurality of physical channels, associating an emulated channel from a plurality of emulated channels for each of the plurality of physical channels, thereby generating a plurality of emulated channels, each of the plurality of emulated channels having a virtual channel identifier, mapping the plurality of emulated channels on a communications link, thereby generating an emulated channel path for each of the plurality of emulated channels, defining a queue pair link buffer from a plurality of queue pair link buffers for each of the emulated channels and increasing a number of queue pair link buffers.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Richard K. Errickson, Thomas A. Gregg, John S. Houston, Ambrose A. Verdibello, Jr.
  • Publication number: 20140164644
    Abstract: An energy management system for a data center network may include a central computer to establish an energy use policy for the computer data center network. The system may also include computer nodes in the computer data center network to receive a packet which is a query that obtains energy information from the nodes and/or a transmission reservation that provides instructions for the energy use policy to be implemented at the computer nodes. The computer nodes may reallocate data traffic on the computer data center network based on the energy use policy to improve energy consumption of the computer data center network.
    Type: Application
    Filed: December 8, 2012
    Publication date: June 12, 2014
    Applicant: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Thomas A. Gregg, Rajaram B. Krishnamurthy, Anuradha Rao
  • Patent number: 8745292
    Abstract: A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters at I/O adapter addresses, the I/O hub including logic for implementing a method comprising receiving requests from the plurality of I/O adapters, storing the I/O adapter addresses of a requester along with their corresponding target recipient addresses and operation codes, receiving a response from a responder, the response indicating that a request has been completed, determining that the response is in a format other than a format supported by the I/O bus, transforming the response into the format supported by the I/O bus, locating a stored I/O adapter address having a corresponding target recipient address that matches the responder address and a corresponding operation code that matches the responder operation code, and transmitting the response to the stored I/O adapter address.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Eric N. Lais, David F. Craddock, Thomas A. Gregg
  • Patent number: 8737228
    Abstract: Flow control in a data center Ethernet (DCE) network is managed between a source node and a destination node separated by an extended distance. An initiation sequence between the source node and the destination node is intercepted. The imitation sequence is for determining buffer credits available for receiving packets in the source node and the destination node. Replies are generated to the source node and the destination node indicating buffer credits available in at least one extended data interface interspersed between the source node and the destination node. The initiation sequence is completed based on the replies from the extended data interface.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Casimer DeCusatis, Thomas A. Gregg
  • Patent number: 8726289
    Abstract: A method of streaming attachment of hardware accelerators to a computing system includes receiving a stream for processing, identifying a stream handler based on the received stream, activating the identified stream handler, and steering the stream to an associated hardware accelerator.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Rajaram B. Krishnamurthy, Thomas A. Gregg
  • Publication number: 20140129796
    Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.
    Type: Application
    Filed: December 2, 2013
    Publication date: May 8, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais
  • Patent number: 8700959
    Abstract: Embodiments of the invention relate to scalable input/output (I/O) function level error detection, isolation, and reporting. An aspect of the invention includes detecting an error in a communication initiated between the function and a system memory, the communication including an I/O request from an application. Future communication is prevented between the one function and the system memory in response to the detecting. The application is notified that the error in communication occurred in response to the detecting.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
  • Publication number: 20140101400
    Abstract: An instruction is provided that includes an opcode field to identify a store instruction to store in a designated location current values of operational parameters of an adapter function of an adapter; a first field to identify a location, the contents of which include a function handle identifying a handle of the adapter function for which the store instruction is being performed, and an indication of an address space associated with the adapter function identified by the function handle to which the store instruction applies; and a second field to identify the designated location of where a result of the store instruction is to be stored. Execution of the instruction includes obtaining information from a function information block associated with the adapter function; and copying the information from the function information block into the designated location, based on completion of one or more validity checks with one or more predefined results.
    Type: Application
    Filed: December 11, 2013
    Publication date: April 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Craddock, Mark S. Farrell, Beth A. Glendening, Thomas A. Gregg, Dan F. Greiner, Gustav E. Sittmann, III, Peter K. Szwed
  • Patent number: 8683108
    Abstract: A method for implementing connected input/output (I/O) hub configuration and management includes configuring a first I/O hub in wrap mode with a second I/O hub. The hubs are communicatively coupled via a wrap cable. The method further includes generating data traffic on a computing subsystem that includes the hubs. Generating traffic includes: converting, via the first hub, a request to implement a transaction into an I/O device-readable request packet and transmitting the request packet over the wrap cable; converting, via the second hub, the I/O device-readable (IODR) request packet into a system readable request and transmitting the request over a system bus; converting, via the second hub, the response to an IODR response packet, and transmitting the response packet over the wrap cable; and converting, via the first hub, the IODR response packet into a system readable response packet, and transmitting the response packet over the system bus.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gerd K. Bayer, Beth A. Glendening, Thomas A. Gregg, Michael Jung, Elke G. Nass, Peter K. Szwed
  • Patent number: 8677180
    Abstract: A system and a method for failover control comprising: maintaining a primary device table entry (DTE) in a first table activated for a first adapter in communication with a first processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in standby for a second adapter in communication with a second processor node having a second root complex via a second switch assembly; maintaining a primary DTE in a second table activated for the second adapter and maintaining a secondary DTE in standby for the first adapter; and upon a failover, updating the secondary DTE in the first table as an active entry for the second adapter and forming a path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first processor node.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gerd K. Bayer, David F. Craddock, Thomas A. Gregg, Michael Jung, Andreas Kohler, Elke G. Nass, Oliver G. Schlag, Peter K. Szwed