Abstract: The present method discloses the steps to form metal device contact studs between regions of a semiconductor device, such as an NPN vertical bipolar transistor, and the first level metal, the studs overlapping both a contact region (such as the base or the collector) and an adjacent polyimide-filled trench. The method is comprised of the following steps:(a) applying a lift off mask exposing said contact region and adjacent trench without attacking the polyimide fill,(b) blanket depositing the stud forming metal onto the whole structure,(c) lifting off said mask and the overlying metal,(d) blanket depositing a second dielectric layer onto the whole structure, the thickness of said second layer being approximately the stud height,(e) removing said second dielectric layer until the top surface of the highest contact stud is exposed and(f) polishing both the metal and said second dielectric layer to leave a substantially planarized structure ready for further personalization.

Abstract: A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls by precluding significant variation in etch bias during the trench formation.

Abstract: A differential reactive ion etching process significantly reduces the reflectivity of silicon. The process takes place in a reactive ion etching tool, typically a diode-configured system employing ambient gases which react with the silicon.