Abstract: A multiphase synthetic ripple voltage generator for a multiphase DC-DC regulator including a master clock circuit that generates a master clock signal, sequence logic and a ripple regulator for each phase. The DC-DC regulator includes multiple switching circuits, each responsive to a corresponding PWM signal to switch input voltages via a phase node through an output inductor to develop an output voltage. The sequence logic sets each PWM signal in sequential order based on the master clock signal. Each ripple generator includes a transconductance amplifier, a ripple capacitor and a comparator. The transconductance amplifier has an input coupled to a corresponding output inductor and an output coupled to a corresponding ripple capacitor. The comparator has a first input coupled to the ripple capacitor, a second input receiving an error voltage, and an output coupled to the sequence logic for resetting a corresponding PWM signal.

Abstract: A multiphase ripple voltage regulator generator employs a hysteretic comparator referenced to upper and lower voltage thresholds. The hysteretic comparator monitors a master ripple voltage waveform developed across a capacitor supplied with a current proportional to the difference between the output voltage and either the input voltage or ground. The output of the hysteretic comparator generates a master clock signal that is sequentially coupled to PWM latches, the states of which define the durations of respective components of the synthesized ripple voltage. A respective PWM latch has a first state initiated by a selected master clock signal and terminated by an associated phase voltage comparator that monitors a respective phase node voltage.

Abstract: A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.

Abstract: A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.

Abstract: A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.

Abstract: A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.

Abstract: A circuit includes a plurality of DC-to-DC converter circuits and separates in time switching of the respective power switches of the DC-to-DC converter circuits which would otherwise be switching at nearly a same time, such as based upon a same desired output level. The switching time may be separated by inverting a periodic control waveform of at least one of the DC-to-DC converter circuits. The multiple output DC-to-DC converter circuit thereby provides an increased noise margin and operates with greater accuracy and stability. The circuit may also determine when the DC-to-DC converter circuits would otherwise be switching at nearly the same time, and activate the switching time separation responsive thereto. For example, the determination may be made based upon a selectable output level being within a predetermined range of at least one other output level.

Abstract: An integrated circuit sample-and-hold (S/H) circuit includes an amplifier offset compensation circuit for compensating for the D.C. offset of a buffer amplifier. The amplifier offset compensation circuit may include an offset determining circuit for determining an offset voltage generated by the buffer amplifier, and an offset correction circuit for generating an offset correction signal and coupling the offset correction signal to the buffer amplifier. The S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and a first field-effect transistor (FET) formed on the substrate. The first FET may have a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the first sampling capacitor during a sampling time and for disconnecting the input signal from the first sampling capacitor during a holding time.

Abstract: A linear voltage regulator includes a pass device for supplying current to a load, and an error amplifier for generating a control signal for controlling the pass device for regulating an output voltage at the load. The error amplifier is connected to a first power supply having a first voltage and a second power supply having a second voltage greater than the first voltage. The error amplifier preferably includes an output stage for providing a greater amount of current to the pass device from the first power supply than from the second power supply when the control signal is below a predetermined value, and for providing a greater amount of current to the pass device from the second power supply than the first power supply when the control signal is above the predetermined value. The predetermined value may be slightly above the typical drive or control voltage needed for a bipolar pass device.

Abstract: An integrated S/H circuit includes a first field-effect transistor (FET) formed on a substrate with a sampling capacitor, and a buffer amplifier having an input connected to the sampling capacitor and an output connectable to the body of the first FET. The buffer amplifier thereby reduces undesired effects from a parasitic diode formed by the body and sampling capacitor. More particularly, the first FET preferably has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time, and for disconnecting the input signal from the sampling capacitor during a holding time. The circuit may include one or more switches for connecting the body of the first FET to the output of the buffer amplifier during the holding time to thereby apply a holding voltage from the sampling capacitor to the body of the first FET.

Abstract: A level shifter for shifting a digital signal input voltage to a digital signal output voltage and for rejecting voltage variations in the level shifter that would cause the level shifter to shift in error. The level shifter includes a trigger for triggering a pulse at each transition of the digital signal between an input supply voltage and an input reference voltage, a latch for switching the digital signal to one of an output supply voltage and an output reference voltage in response to each pulse from the driver and holding the digital signal at that voltage, and two half-shifters connected between the trigger and the latch for providing the pulse to said latch when the digital signal transitions. Each of the half-shifters include a selector circuit with series-connected current mirrors connected to a current source for providing a current to the current mirrors responsive to receipt of the pulse.

Abstract: A system includes an upper driver circuit connected between a first source of voltage and a first point of reference potential, for driving the gate of a first switching device having a main current path connected between a second source of operating voltage and the first point of reference potential. The system further includes a lower driver circuit connected between a third source of operating voltage and a second point of reference potential, for driving the gate of a second switching device having a main current path connected between the first and second points of reference potential. Detection circuitry is included for detecting a common-mode dv/dt induced signal to disable the sensing of valid "ON" and "OFF" signals by the upper circuit, to prevent false triggering of the upper circuit.

Abstract: An electronic metering circuit includes a current transformer having active feedback for maintaining core flux near zero. In one embodiment of the invention, DC offset-voltage compensation in an operational amplifier providing the active-feedback signal is accomplished using an integrator having a long time constant compared to the time constant of periodic signals. A further embodiment of the invention integrates the functions of current sensing, DC offset-voltage compensation, and part of the switching function required in the electronic metering circuit.