Abstract: An apparatus for invalidating redundant entries in an N-way set associative branch target address cache (BTAC) for the same branch instruction is disclosed. An index portion of an instruction cache fetch address is applied to the BTAC to select a set of N ways therein. Control logic detects a condition in which more than one of the N ways of the selected set has a valid tag that matches the tag portion of the fetch address. A flag is set to indicate the occurrence of the condition, and the fetch address is stored in a register. The control logic subsequently invalidates all but one of the N ways having a valid tag that matches the fetch address tag.

Abstract: The present invention provides isolated monoclonal antibodies that selectively bind albumin from animals. Also provided are methods using such antibodies for the detection of early renal disease in animals. The method includes the steps of (a) obtaining a sample from an animal to be tested; (b) contacting the sample with an antibody having a greater avidity for feline albumin than for other proteins or components in the sample; (c) detecting the complex formed by the antibody and albumin; and (d) determining the amount of albumin in the sample from the amount of antibody-albumin complex detected. An amount of albumin in the range of from 10 ?g/ml to about 300 ?g/ml indicates the presence of early renal disease.

Abstract: A guard and associated method for rain gutters includes a cap or deflector extending over a gutter of the type having a trough-shaped interior, a rear wall extending along a roof fascia, and a front lip with a channel and an end flange. A mounting bracket has a rear portion abutting the rear wall of the gutter, an upper portion supporting the deflector, and a front portion with a hook-shaped nose. The mounting bracket nose is configured for insertion under the end flange of the gutter, such that the mounting bracket is rotated rearwardly along a generally vertical arc about the nose toward the rear wall of the gutter, and shifted laterally into a skewed orientation within the gutter interior.

Abstract: An apparatus for killing an instruction after it has already been loaded into an instruction queue of a microprocessor is disclosed. The apparatus includes control logic that detects a condition in which the instruction must not be executed, such as a branch instruction misprediction; however, the control logic determines the condition too late to prevent the instruction from being loaded into the instruction queue. The control logic generates a kill signal indicating the instruction must not be executed. A kill queue receives the kill signal and stores its value. The kill queue maintains its entries in parallel with the instruction queue entries so that when the instruction queue subsequently outputs the instruction, the kill queue also outputs the value of the kill signal associated with the, instruction. If the kill signal value output from the kill queue is true, then the microprocessor invalidates the instruction and does not execute it.

Abstract: A vented soffit panel and related method for buildings and the like includes a generally flat imperforate base portion shaped to enclose at least a portion of the building soffit when mounted in a generally horizontal orientation under an eave. At least one vent channel protrudes upwardly from the base portion, and has a generally trapezoidal shape defined by a horizontal imperforate top wall and inclined perforate sidewalls with lower ends that connect with the base portion in a spaced apart relationship to define a slot through which air flows to vent the eave. The perforate sidewalls are disposed at an acute angle, such that they are hidden from view from a position underneath the eave.

Abstract: A mat configured to mount at or around the base of a post to prevent vegetation from growing around the post base and facilitates landscaping around the post is disclosed. The mat has a slot that radiates from a center portion to an outer edge. The slot has interlocking slot sides that mate together to form a seamless or nearly seamless appearance. The center portion can be configured to tightly fit around the outer perimeter of the post. A post cone may be added to or integrally formed with the mat. The post cone extends vertically up the post and provides additional contact area between the post and the mat. Preferably the mats is flexible, maintains its shape during exposure, and thin enough to not interfere with landscaping equipment, but thick enough to provide sufficient weight to allow the mat to maintain contact with the ground.

Abstract: A chilled beverage dispenser has a “holeless” bowl and uses a cradle evaporator to achieve cooling of the beverage. In one exemplary embodiment, the cradle evaporator comprises three panels—a bottom panel and two side panels, the side panels being bolted or similarly fastened to the edges of the bottom panel in a substantially perpendicular orientation relative to the bottom panel. The bottom and side panels each define a continuous and sinuous channel, which carries a cooling medium. The dispenser bowl preferably is constructed of a thin-walled plastic, such that when the dispenser bowl is received in the cradle evaporator, heat transfer is achieved through the bottom wall and portions of the side walls of the bowl.

Abstract: A guard and associated method for rain gutters includes a cap or deflector extending over a gutter of the type having a trough-shaped interior, a rear wall extending along a roof fascia, and a front lip with a channel and an end flange. A mounting bracket has a rear portion abutting the rear wall of the gutter, an upper portion supporting the deflector, and a front portion with a hook-shaped nose. The mounting bracket nose is configured for insertion under the end flange of the gutter, such that the mounting bracket is rotated rearwardly along a generally vertical arc about the nose toward the rear wall of the gutter, and shifted laterally into a skewed orientation within the gutter interior.

Abstract: A genomic nucleotide sequence encoding Serum Amyloid A (SAA), isolated and purified from mammalian colostrum, is disclosed. Methods of use for the same in transgenic protocols is also disclosed.

Abstract: A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.

Abstract: A branch prediction apparatus having two two-way set associative cache memories each indexed by a lower portion of an instruction cache fetch address is disclosed. The index selects a group of four entries, one from each way of each cache. Each entry stores a single target address of a different previously executed branch instruction. For some groups, the four entries cache target addresses for one branch instruction in each of four different cache lines, to obtain four-way group associativity; for other groups, the four entries cache target addresses for one branch instruction in each of two different cache lines and two branch instructions in a third different cache line, to effectively obtain three-way group associativity, depending on the distribution of the branch instructions in the program. The apparatus trades off associativity for number of predictable branches per cache line on an index-by-index basis to efficiently use storage space.

Abstract: An optical orientation piece for use with reflector telescopes for the rotation of the viewed image at the eyepiece to allow for land based viewing. The orientation piece comprises a housing with standard optical interfaces to allow it to be inserted between the telescope focusing mechanism and the eyepiece. The orientation piece design allows it to be rotated about the axis of the telescope drawtube to a point at which the reflected image appears properly oriented to the users real world viewing. The device is capable of rotating the image to any desired angle.

Abstract: A method and apparatus are provided for processing far jump-call branch instructions within a processor in a manner which reduces the number of stalls of the processor pipeline. The processor includes an apparatus, for providing a fallback far jump-call speculative target address that corresponds to a current far jump-call branch instruction. The microprocessor apparatus includes a far jump-call branch target buffer and a fallback speculative target address generator. The far jump-call branch target buffer stores a plurality of code segment bases and offsets corresponding to a plurality of previously executed far jump-call branch instructions, and determines if a hit for the current far jump-call branch instruction is contained therein. The fallback speculative target address generator is coupled to the far jump-call branch target buffer.

Abstract: A branch control apparatus in a microprocessor. A register receives a first cache line containing a branch instruction from an instruction cache in response to a fetch address. The fetch address hits in a BTAC that provides a target address of the branch instruction. The BTAC also provides an offset of the instruction following the branch instruction. The instructions following the branch instruction are invalidated based on the offset. Muxing logic packs only the valid instructions into a byte-wide instruction buffer that is directly coupled to instruction format logic. The instruction cache provides a second cache line containing the target instructions to the register in response to the target address. The instructions preceding the target instructions are invalidated based on the lower bits of the target address. The muxing logic packs only the valid target instructions into the instruction buffer immediately adjacent to the branch instruction bytes.

Abstract: A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.

Abstract: A universal end cap and associated method are provided for rain gutter debris guards of the type having a top cap extending along a roof and over the open top of an associated gutter. The universal end cap includes a generally flat, rigid cover panel with a substantially rectangular lower portion sized to extend over either end of the guard, and is severable to custom fit the end cap to a wide variety of different gutters. A pair of curved nose portions project outwardly from opposite sides of the cover panel adjacent the upper edge thereof, and are configured to close off the forward portion of the top cap at either end thereof. A mounting flange extends along at least a portion of the upper edge of the cover panel, and a retainer fastens the mounting flange to the top cap at either end thereof to prevent debris form entering between the adjacent ends of the gutter and the guard.

Abstract: A vented soffit panel and related method for buildings and the like includes a generally flat imperforate base portion shaped to enclose at least a portion of the building soffit when mounted in a generally horizontal orientation under an eave. At least one vent channel protrudes upwardly from the base portion, and has a generally trapezoidal shape defined by a horizontal imperforate top wall and inclined perforate sidewalls with lower ends that connect with the base portion in a spaced apart relationship to define a slot through which air flows to vent the eave. The perforate sidewalls are disposed at an acute angle, such that they are hidden from view from a position underneath the eave.

Abstract: A guard and associated method for rain gutters includes a cap or deflector extending over a gutter of the type having a trough-shaped interior, a rear wall extending along a roof fascia, and a front lip with a channel and an end flange. A mounting bracket has a rear portion abutting the rear wall of the gutter, an upper portion supporting the deflector, and a front portion with a hook-shaped nose. The mounting bracket nose is configured for insertion under the end flange of the gutter, such that the mounting bracket is rotated rearwardly along a generally vertical arc about the nose toward the rear wall of the gutter, and shifted laterally into a skewed orientation within the gutter interior.

Abstract: A method and apparatus are provided for processing far jump-call branch instructions to increase the efficiency of a processor pipeline. The processor includes a far jump-call target buffer which stores the default address/operand size corresponding to each of a plurality of previously executed far jump-call instructions. When a far jump-call instruction is encountered, it is speculatively executed using the corresponding default address/operand size for that instruction as stored in the far jump-call target buffer. This speculative far jump-call instruction is executed and resolved thus determining the actual address/operand size. If the actual address/operand size matches the speculative default address/operand size then the speculation was correct and processing continues. However, if there is no match, then the speculation was wrong and the pipeline is flushed.

Abstract: An apparatus for speculatively predicting the direction of a branch instruction in a pipelined microprocessor in a hybrid fashion. A branch target address cache (BTAC) stores a direction prediction about executed branch instructions. The BTAC is indexed by an instruction cache fetch address. The BTAC is accessed in parallel with the instruction cache access, such that the direction prediction is provided before the actual instruction is decoded which is presumed to be a branch instruction corresponding to the direction prediction stored in the BTAC. In parallel with the BTAC access, a branch history table (BHT) is accessed to provide a second speculative direction prediction. The BHT is indexed with a gshare function of the instruction cache fetch address and a global branch history stored in a global branch history register. The BTAC also provides a selector that selects between the two speculative direction predictions.