Abstract: Disclosed herein are techniques for performing multi-layer neural network processing for multiple contexts. In one embodiment, a computing engine is set in a first configuration to implement a second layer of a neural network and to process first data related to a first context to generate first context second layer output. The computing engine can be switched from the first configuration to a second configuration to implement a first layer of the neural network. The computing engine can be used to process second data related to a second context to generate second context first layer output. The computing engine can be set to a third configuration to implement a third layer of the neural network to process the first context second layer output and the second context first layer output to generate a first processing result of the first context and a second processing result of the second context.

Abstract: Access control request parameter interleaving may be implemented that supports user-configurable and host-configurable processing stages. A request may be received and evaluated to determine whether user-configured interleaving, host-configured interleaving, or both user-interleaving and host-interleaving are applied. For applied interleaving, two different portions of a request parameter may be swapped.

Abstract: Disclosed herein are techniques for scheduling and executing multi-layer neural network computations for multiple contexts. In one embodiment, a method comprises determining a set of computation tasks to be executed, the set of computation tasks including a first computation task and a second computation task, as well as a third computation task and a fourth computation task to provide input data for the first and second computation tasks; determining a first execution batch comprising the first and second computation tasks; determining a second execution batch comprising at least the third computation task to be executed before the first execution batch; determining whether to include the fourth computation task in the second execution batch based on whether the memory device has sufficient capacity to hold input data and output data of both of the third and fourth computation; executing the second execution batch followed by the first execution batch.

Abstract: On-circuit data activity monitoring may be performed for a systolic array. A current data activity measurement may be determined for changes in input data for processing at a systolic array and compared with a prior data activity measurement. Based on the comparison, a throttling recommendation may be provided to a management component to determine whether to perform the throttling recommendation.

Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each row of the systolic array can include multiple busses enabling independent transmission of inputs along the respective bus. Each processing element can include a plurality of interconnects to receive a plurality of inputs corresponding to the multiple busses. Each processing element of a given row-oriented bus can receive an input from a prior element of the given row-oriented bus at an active bus position and perform arithmetic operations on the input. Each processing element can further receive a plurality of inputs at passive bus positions and provide the plurality of inputs to subsequent processing elements without the plurality of inputs being processed by the processing element. Use of row-oriented busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

Abstract: An integrated circuit includes a processing engine configured to execute instructions that are synchronized using a set of events. The integrated circuit also includes a set of event registers and an age bit register. Each event in the set of events corresponds to a respective event register in the set of event registers. The age bit register includes a set of age bits, where each age bit in the age bit register corresponds to a respective event register in the set of event registers. Each age bit in the age bit register is configured to be set by an external circuit and to be cleared in response to a value change in a corresponding event register in the set of event registers. Executing the instructions by the processing engine changes a value of an event register in the set of event registers.

Abstract: Alternative reporting channels are implemented for interrupts to a microcontroller device. An access device for a microcontroller may support performing requests from a microcontroller to controlled devices via an interconnect. The access device may have a separate communication channel with at least one of the controlled devices to receive interrupts. When an interrupt is signaled, an indication of the interrupt may be stored at a storage device at the access device. The microcontroller may read from the storage device at the access device to obtain the indication of the interrupt.

Abstract: To reduce power consumption, data bits or a portion of a data register that is not expected to toggle frequently can be grouped together, and be clock-gated independently from the rest of the data register. The grouping of the data bits can be determined based on the data types of the workload being operated on. For a data register configured to store a numeric value that supports multiple data types, the portion of the data register being clock-gated may store a group of data bits that are unused for one or more data types of the multiple data types supported by the data register. The portion of the data register being clock-gated can also be a group of data bits that remain unchanged or have a constant value for numeric values within a certain numeric range that is frequently operated on.

Abstract: Clock skew may be increased along a critical path of a systolic array. Pipelined registers may be added between a bus that provides input data signals to a systolic array and between a bus that receives output data signals from the systolic array. Skew circuitry for the pipelined registers may be implemented to delay a clock signal to the pipelined registries to allow a clock skew accumulated along a critical path of the systolic array to exceed a single clock cycle.

Abstract: A circuit at an interface between a device and an interconnect fabric is configured to track outstanding transactions associated with the device and ensure the completion of the outstanding transactions before rebooting or powering down the device. In some embodiments, the circuit is also configurable to provide appropriate responses when the device is powered down or is being rebooted such that other devices in the system can still operate even without knowing that the device is inactive and would not hang because no response is received from the device.

Abstract: Disclosed herein are techniques for tracking usage of a storage-class memory. In one embodiment, a method includes receiving a first statistics update entry and a second statistics update entry by a memory controller for a memory, and assembling the statistics update entries into a statistics log entry. The first statistics update entry indicates a number of operations performed on a first memory block in the memory, and the second statistics update entry indicates a number of operations performed on a second memory block in the memory. The method also includes determining a persistent memory region in a persistent memory for storing the statistics log entry, and writing the statistics log entry into the persistent memory region, where the statistics log entry persists in the persistent memory region until the statistics log entry is read back through the memory controller.

Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each row of the systolic array can include multiple busses enabling independent transmission of inputs along the respective bus. Each processing element of a given row-oriented bus can receive an input from a prior element of the given row-oriented bus, and perform arithmetic operations on the input. Each processing element can generate an output partial sum based on the arithmetic operations, provide the input to a next processing element of the given row-oriented bus, without the input being processed by a processing element of the row located between the two processing elements that uses a different row-oriented bus. Use of row-oriented busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each column of the systolic array can include multiple busses enabling independent transmission of input partial sums along the respective bus. Each processing element of a given columnar bus can receive an input partial sum from a prior element of the given columnar bus, and perform arithmetic operations on the input partial sum. Each processing element can generate an output partial sum based on the arithmetic operations, provide the output partial sum to a next processing element of the given columnar bus, without the output partial sum being processed by a processing element of the column located between the two processing elements that uses a different columnar bus. Use of columnar busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

Abstract: An integrated circuit is configurable to generate a notification message when an indicator of an event used to synchronize the execution of different functional blocks of the integrated circuit changes status. The indicator of the event is cleared when an operation is triggered and is set when the operation completes. The notification message includes a timestamp indicating the time when the indicator of the event changes status. The notification message is used to determine the execution timeline of a set of instructions executed by integrated circuit and to identify bottlenecks in the set of instructions or the integrated circuit.

Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each column of the systolic array can include multiple busses enabling independent transmission of input partial sums along the respective bus. Each processing element can include a plurality of interconnects to receive a plurality of inputs corresponding to the multiple busses. Each processing element of a given columnar bus can receive an input from a prior element of the given columnar bus at an active bus position and perform arithmetic operations on the input. Each processing element can further receive a plurality of inputs at passive bus positions and provide the plurality of inputs to subsequent processing elements without the plurality of inputs being processed by the processing element. Use of columnar busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

Abstract: Access control request parameter remapping may be implemented that supports user-configurable and host-configurable processing stages. A request may be received and evaluated to determine user-configured remapping is applied, host-configured remapping is applied or both user and host remapping applied. For applied remapping, an unmasked portion of a parameter of the access request may be replaced with a corresponding portion of a remap parameter.

Abstract: Disclosed are devices, systems, and methods for the use of memory including a data table configured to store a plurality of elements, wherein the plurality of elements are arranged into a plurality of buckets and each of the plurality of buckets comprising a plurality of entries. A first power domain can be associated with an entry of each bucket or with a first bucket. A second power domain can be associated with a second entry of each bucket or a second bucket. Processing logic can be configured to search for a particular value stored in an element of the plurality of elements by selecting buckets of the plurality of buckets and selecting at least one entry of each of the buckets. A programmable register can be used to select a powered state of the second power domain based on a configuration of the programmable register.

Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each row of the systolic array can include multiple busses enabling independent transmission of inputs along the respective bus. Each processing element of a given row-oriented bus can receive an input from a prior element of the given row-oriented bus, and perform arithmetic operations on the input. The systolic array can be divided into a plurality of sub-arrays corresponding to a row-oriented bus where each sub-array is separated by a shifter. Each shifter can shift a row-oriented bus into the active bus position for a given sub-array. Use of row-oriented busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

Abstract: Disclosed are techniques for generating and examining a signature that corresponds to a plurality of data packets. The data packets can be packets forwarded by a network device. By examining the signature, information pertaining to the plurality of data packets can be determined. A determination can be made if one of the plurality of data packets is not received by the network device.

Abstract: An access device may be implemented to provide one or more access channels to non-volatile memory. Memory mapping implemented at the access device may direct a memory controller of the access device to perform access requests, replacing an initial storage location with a different storage location to access in the non-volatile memory device. Address scrambling, encryption, and other modifications to performing an access request may be implemented at the access device, in some embodiments, in addition to the memory mapping techniques.