Abstract: Provided are systems and methods for implementing a memory for an integrated circuit device. In various examples, the integrated circuit can operate the memory as a FIFO, where each address in the FIFO is directly addressable. The integrated circuit can include a first register for storing a head pointer and a second register for storing a tail pointer. When new data is written to the memory, the data cat be written starting at the tail pointer location, without the tail pointer being modified. The tail pointer can be incremented using write transactions received from external to the integrated circuit.

Abstract: A circuit at an interface between a device and an interconnect fabric is configured to track outstanding transactions associated with the device and ensure the completion of the outstanding transactions before rebooting or powering down the device. In some embodiments, the circuit is also configurable to provide appropriate responses when the device is powered down or is being rebooted such that other devices in the system can still operate even without knowing that the device is inactive and would not hang because no response is received from the device.

Abstract: Packet processors or other devices with packet processing pipelines may implement pipelined evaluations of algorithmic forwarding route lookups. As network packets are received, a destination address for the network packets may be divided into different possible prefix lengths and corresponding entries in a routing table for the different possible prefix lengths may be determined according to a hash scheme for the routing table. The entry values may be read from the routing table and evaluated at subsequent stages to identify the entry with a longest prefix match with respect to the destination address for the network packet. The routing table may include entries for different types of network packets and may be configured to include virtual routing and forwarding for network packets.

Abstract: Provided are systems and methods for an integrated circuit comprising a search engine, which a memory controller can use to manage a page table. In various implementations, the search engine can generate a series of read transactions to read the page table, which is stored in a memory. Each page table entry includes an address translation for processor memory. The memory controller may periodically change the address translations. The search engine can further determine whether data read from an entry in the page table corresponds to a search parameter. The search engine can further output a response, where the response is affirmative when the data read from the entry corresponds to the search parameters, and where the response is negative when no data read from any entry corresponds to the search parameter.

Abstract: Provided are systems and methods for an address translation circuit for a memory controller. The address translation circuit can include an address translation table. A first set of rows in the address translation table can be associated with all virtual machine identifiers supported by the memory controller. A second set of rows can be associated with only a particular virtual machine identifier. The address translation circuit can receive an input address for a transaction to processor memory. The address translation circuit can determine an index by inputting the input address into a hash function. The address translation circuit can read a row from the address translation table using the index. The address translation circuit can determine whether an entry in the row includes the address translation for the input address. The address translation circuit can generate and output a translated address using the address translation.

Abstract: A contiguous region in memory may be configured to store data so that a first portion of the data is addressable using a first indexing scheme and a second portion of the data is addressable using a second indexing scheme. The first portion of the data may include information which may be used by one entity and the second portion of the data may include different information which may be used by another entity.

Abstract: Disclosed herein are techniques for management of a non-volatile memory device. In one embodiment, an integrated circuit includes a cache device and a cache controller. The cache device stores a mapping between a physical addresses of a memory device and a logical address, and a counter associated with the physical address. The cache controller is configured to: receive an address translation request to translate a first logical address; identify, from the cache device, a first entry that stores a first mapping between the first logical address and a first physical address; and based on a determination that the address translation request is for a pre-determined type of operation for the first physical address, update a first counter stored in the first storage unit. The cache controller can transmit a value of the first counter to a management controller for performing a pre-determined wear-leveling operation for the memory device.

Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

Abstract: External memory protection may be implemented for content addressable memory (CAM). Memory protection data, such as duplicate values for entries in a CAM or error detection codes generated from values of the entries in a CAM, may be stored in a random access memory that is separate from the CAM. When an entry in the CAM is accessed to perform a lookup or scrubbing operation, the memory protection data may be obtained from the RAM. A validation of the value of the entry may then be performed according to the memory protection data to determine whether the value is valid.

Abstract: An integrated circuit includes a processing engine configured to execute instructions that are synchronized using a set of events. The integrated circuit also includes a set of event registers and an age bit register. Each event in the set of events corresponds to a respective event register in the set of event registers. The age bit register includes a set of age bits, where each age bit in the age bit register corresponds to a respective event register in the set of event registers. Each age bit in the age bit register is configured to be set by an external circuit and to be cleared in response to a value change in a corresponding event register in the set of event registers. Executing the instructions by the processing engine changes a value of an event register in the set of event registers.

Abstract: Disclosed are techniques for implementing packet checkers and packet generators within a network device. The packet checkers and packet generators can each operate in an internal mode to test functionality of the network device or in an external mode to test functionality of an external device.

Abstract: Disclosed are techniques for implementing network devices with pluralities of packet checkers or packet generators. The packet generators can be configured to self generate data packets with a packet payload and header information and a test type of data packets. The packet checkers can determine if a data packet is a test type of data packet and perform one or more actions.

Abstract: A microcontroller may be implanted to manage migration events performed by a separate memory controller to non-volatile memory. Migration events, such as failed writes at the memory controller or wear leveling migrations to move data from one storage location to another may be detected by the microcontroller. The destination location and the data to be migrated may be identified by the microcontroller. The microcontroller may then instruct the memory controller to copy the data to the destination location.

Abstract: Provided are systems and methods for modifying a forwarding decision for a packet being processed by a network device. The forwarding decision can include a final determination whether to forward the packet from the network device and onto a network. In various implementations, an integrated circuit device of the network device can receive packet information for the packet, where the packet information includes a forwarding decision. The forwarding decision can include a decision type. The integrated circuit device can further determine a redirection includes using the decision type. The redirection information can include a redirection entry for each of one or more decision types. The integrated circuit device can further modify the packet information using values from the particular redirection entry, excluding modification of values associated with an outbound packet header that can be used to forward the particular packet.

Abstract: In one embodiment of the disclosure, packets are routed according to a VRF (Virtual Routing and Forwarding) domain that is represented by a VRF identifier in a VRF-identifier (ID) field of packet headers. In one embodiment of the disclosure, a VRF identifier may be added to a VRF-ID field of a packet header so that the packet is routed according to a VRF domain that the packet belongs to.

Abstract: Destination resolution stages that determine a forwarding decision for a network packet may be selected. Different resolution stages in a packet processing pipeline may be individually identified. Upon accessing an entry in a lookup table in a stage of the packet processing pipeline, a pointer type of a pointer in the entry may identify a next destination resolution stage for determining the forwarding decision of a network packet. Different types of network packets may have forwarding decisions determined using different destination resolution stages, one or more shared resolution stages, or the same resolution stages.

Abstract: Disclosed herein are techniques for monitoring the performance of a storage-class memory (SCM). In some embodiments, a performance monitoring circuit at an interface between the SCM and a memory controller of the SCM receives transaction commands from the memory controller to the SCM, measures statistics associated with the transaction commands, and determines a utilization rate of the SCM based on the statistics. Based on the determined utilization rate of the SCM, future transaction requests can be optimized to improve the utilization rate of the SCM.

Abstract: Disclosed are techniques for implementing features within a network device. The network device can function to forward sequences of data packets received by the network device as well as concurrently generate or check test type of data packets.

Abstract: Packet processing pipelines may implement filtering of control plane decisions. When network packets are received various types of decision-making and processing is performed. In order to complete processing for the network packet, some decisions may need to be determined by a control plane for the packet processing pipeline, such as a general processor. Requests for control plane decisions for received network packets may be filtered prior to sending the requests to the control plane based on whether the same control plane decisions have been requested for previously received network packets. For control plane decisions with outstanding control plane decision requests, an additional control plane decision request for the network packet may be blocked, whereas control plane decisions with no outstanding control plane decision requests may be allowed.

Abstract: Provided are systems and methods for managing historically large flows in network visibility monitoring. In some implementations, provided is an integrated circuit. The integrated circuit may be operable to receive packet information describing a packet at the cycle of a clock input. The packet may be associated with a packet flow being transmitted across a network. The integrated circuit may further generate keys using information identifying a packet flow provided by the packet information. The integrated circuit may further read values for counters and state information associated with each counter from a memory, using the keys. The integrated circuit may further determine from the state information that the packet flow identified by the packet information is a historically large packet flow. Upon determining that the packet flow is a historically large packet flow, the integrated circuit may further update an entry in a flow memory using the packet information.