Patents by Inventor Thomas A. Wallner
Thomas A. Wallner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8787074Abstract: A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.Type: GrantFiled: October 14, 2011Date of Patent: July 22, 2014Assignee: International Business Machines CorporationInventors: Oliver D. Patterson, Jin Zheng Wallner, Thomas A. Wallner, Shenzhi Yang
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Publication number: 20130333697Abstract: This disclosure describes methods and apparatus for indicating battery cell status on a battery pack assembly used during mechanical ventilation. Embodiments described herein seek to provide methods for indicating battery cell status on the exposed exterior of a battery assembly pack both when the battery is in use and when the battery is not in use during mechanical ventilation. Embodiments utilize power from the ventilator as well as power from the battery pack itself to light the indicators during periods of battery use and non-use, respectively. Embodiments described herein further seek to provide an apparatus indicating battery cell status on the exposed exterior of the battery pack assembly during mechanical ventilation. Embodiments described herein further seek to provide an apparatus for a battery pack assembly used during mechanical ventilation. Embodiments described herein seek to provide a system for a ventilation system with an inserted battery pack assembly.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Covidien LPInventors: Danis Carter, Terry Landis, Thomas Wallner, John Leek
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Patent number: 8569840Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: GrantFiled: February 10, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
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Publication number: 20130256748Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William F. Clark, JR., Robert J. Gauthier, JR., Terence B. Hook, Junjun Li, Theodorus E. Standaert, Thomas A. Wallner
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Patent number: 8547062Abstract: This disclosure describes methods and apparatus for indicating battery cell status on a battery pack assembly used during mechanical ventilation. Embodiments described herein seek to provide methods for indicating battery cell status on the exposed exterior of a battery assembly pack both when the battery is in use and when the battery is not in use during mechanical ventilation. Embodiments utilize power from the ventilator as well as power from the battery pack itself to light the indicators during periods of battery use and non-use, respectively. Embodiments described herein further seek to provide an apparatus indicating battery cell status on the exposed exterior of the battery pack assembly during mechanical ventilation. Embodiments described herein further seek to provide an apparatus for a battery pack assembly used during mechanical ventilation. Embodiments described herein seek to provide a system for a ventilation system with an inserted battery pack assembly.Type: GrantFiled: April 9, 2010Date of Patent: October 1, 2013Assignee: Covidien LPInventors: Danis Carter, Terry Landis, Thomas Wallner, John Leek
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Patent number: 8424523Abstract: This disclosure describes systems and methods for ventilating a patient with a system that includes an accumulator for storing a gas mixture. This disclosure describes systems and methods for ventilating a patient with a system that includes an accumulator located away from the flow path that reduces/eliminates pockets of an undesirable gas mixture from entering the gas flow path and reaching the patient after a gas mixture change by utilizing a purge valve.Type: GrantFiled: March 23, 2010Date of Patent: April 23, 2013Assignee: Covidien LPInventors: Mark Ogilvie, Steve Vuong, Nirav Patel, Richard Nakai, Thomas Wallner
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Publication number: 20130094315Abstract: A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.Type: ApplicationFiled: October 14, 2011Publication date: April 18, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oliver D. Patterson, Jin Zheng Wallner, Thomas A. Wallner, Shenzhi Yang
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Publication number: 20120326168Abstract: A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.Type: ApplicationFiled: September 10, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas N. Adam, Judson R. Holt, Alexander Reznicek, Thomas A. Wallner
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Publication number: 20120319166Abstract: A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas N. Adam, Judson R. Holt, Alexander Reznicek, Thomas A. Wallner
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Patent number: 8232172Abstract: Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.Type: GrantFiled: March 11, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Judson R. Holt, Thomas A. Wallner
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Publication number: 20120139056Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: ApplicationFiled: February 10, 2012Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
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Patent number: 8129234Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: GrantFiled: September 9, 2009Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
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Patent number: 8124534Abstract: A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.Type: GrantFiled: July 22, 2008Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Jin Wallner, Thomas A. Wallner, Ying Zhang
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Patent number: 8062951Abstract: An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.Type: GrantFiled: December 10, 2007Date of Patent: November 22, 2011Assignee: International Business Machines CorporationInventors: Xiangdong Chen, Kenneth J. Stein, Thomas A. Wallner
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Publication number: 20110159655Abstract: Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.Type: ApplicationFiled: March 11, 2011Publication date: June 30, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas N. Adam, Judson R. Holt, Thomas A. Wallner
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Publication number: 20110132366Abstract: This disclosure describes systems and methods for ventilating a patient with a system that includes an accumulator for storing a gas mixture. This disclosure describes systems and methods for ventilating a patient with a system that includes an accumulator located away from the flow path that reduces/eliminates pockets of an undesirable gas mixture from entering the gas flow path and reaching the patient after a gas mixture change by utilizing a purge valve.Type: ApplicationFiled: March 23, 2010Publication date: June 9, 2011Applicant: Nellcor Puritan Bennett LLCInventors: Mark Ogilvie, Steve Vuong, Nirav Patel, Richard Nakai, Thomas Wallner
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Publication number: 20110126829Abstract: This disclosure describes methods and apparatus for indicating battery cell status on a battery pack assembly used during mechanical ventilation. Embodiments described herein seek to provide methods for indicating battery cell status on the exposed exterior of a battery assembly pack both when the battery is in use and when the battery is not in use during mechanical ventilation. Embodiments utilize power from the ventilator as well as power from the battery pack itself to light the indicators during periods of battery use and non-use, respectively. Embodiments described herein further seek to provide an apparatus indicating battery cell status on the exposed exterior of the battery pack assembly during mechanical ventilation. Embodiments described herein further seek to provide an apparatus for a battery pack assembly used during mechanical ventilation. Embodiments described herein seek to provide a system for a ventilation system with an inserted battery pack assembly.Type: ApplicationFiled: April 9, 2010Publication date: June 2, 2011Applicant: Nellcor Puritan Bennett LLCInventors: Danis Carter, Terry Landis, Thomas Wallner, John Leek
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Publication number: 20110057266Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: ApplicationFiled: September 9, 2009Publication date: March 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
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Patent number: 7858485Abstract: A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.Type: GrantFiled: August 14, 2008Date of Patent: December 28, 2010Assignee: International Business Machines CorporationInventors: Huilong Zhu, Babar A. Khan, Xi Li, Joyce C. Liu, Thomas A. Wallner
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Publication number: 20100200896Abstract: A method for growing an epitaxial layer on a substrate wherein the substrate includes a surface having a Miller index of (110) for the beneficial properties. The method comprises using a direct silicon bonded wafer with a substrate having a first Miller index and a surface having a second Miller index. An element such as a gate for a PFET may be deposited onto the surface. The area not under the gate may then be etched away to expose the substrate. An epitaxial layer may then be grown on the surface providing optimal growth patterns. The Miller index of the substrate may be (100). In an alternative embodiment the surface may have a Miller index of (100) and the surface is etched where an element such as a gate for a PFET may be placed.Type: ApplicationFiled: February 9, 2009Publication date: August 12, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas N. Adam, Jinghong Li, Thomas A. Wallner, Haizhou Yin