Patents by Inventor Thomas A. Wassick

Thomas A. Wassick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10586782
    Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Clement J. Fortin, Christopher D. Muzzy, Brian W. Quinlan, Thomas A. Wassick, Thomas Weiss
  • Patent number: 10381276
    Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
  • Patent number: 10249548
    Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
  • Publication number: 20190006312
    Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.
    Type: Application
    Filed: July 1, 2017
    Publication date: January 3, 2019
    Inventors: CHARLES L. ARVIN, Clement Fortin, Christopher D. Muzzy, Brian W. Quinlan, Thomas A. Wassick, Thomas Weiss
  • Patent number: 9947598
    Abstract: A methodology and associated wafer level assembly of testing crackstop structure designs. The wafer level semiconductor assembly includes: a substrate structure shaped to define a set of horizontal directions; a metallization layer located on top of the substrate structure, with the metallization layer including a crackstop structure formed therein in accordance with a crackstop structure design; and a tensioned layer located on top of the metallization layer, with the tensioned layer being made of material having internal tensile forces oriented in the horizontal directions. The tensile forces promote horizontal direction crack propagation in the metallization layer so that the crackstop structure design can be tested more rigorously and reliably before deciding on the crackstop design structure to put into mass production (which mass produced product would typically not include the tensioned layer).
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Krishna R. Tunga, Karen P. McLaughlin, Charles L. Arvin, Brian R. Sundlof, Steven P. Ostrander, Christopher D. Muzzy, Thomas A. Wassick
  • Publication number: 20180076101
    Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
  • Patent number: 9853006
    Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto, Thomas A. Wassick
  • Patent number: 9793232
    Abstract: A standoff structure for providing improved interconnects is provided, wherein the structure employs nickel copper alloy or copper structures having increased resistivity.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Luc Guerin, Sylvain Ouimet, Sylvain Pharand, Thomas A. Wassick
  • Patent number: 9773726
    Abstract: Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Timothy D. Sullivan, Thomas A. Wassick
  • Publication number: 20170178982
    Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
  • Publication number: 20170077021
    Abstract: Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Inventors: Timothy D. Sullivan, Thomas A. Wassick
  • Patent number: 9515035
    Abstract: Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Timothy D. Sullivan, Thomas A. Wassick
  • Patent number: 9477568
    Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Jon A. Casey, Sungjun Chun, Alan J. Drake, Charles R. Lefurgy, Karthick Rajamani, Jeonghee Shin, Thomas A. Wassick, Victor Zyuban
  • Publication number: 20160307860
    Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto, Thomas A. Wassick
  • Patent number: 9396991
    Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: July 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto, Thomas A. Wassick
  • Patent number: 9379007
    Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Charles L. Arvin, Kenneth Bird, Charles C. Goldsmith, Sung K. Kang, Minhua Lu, Clare J. McCarthy, Eric D. Perfecto, Srinivasa S. N. Reddy, Krystyna W. Semkow, Thomas A. Wassick
  • Publication number: 20160181215
    Abstract: Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Timothy D. Sullivan, Thomas A. Wassick
  • Publication number: 20160056072
    Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 25, 2016
    Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto, Thomas A. Wassick
  • Publication number: 20150333025
    Abstract: The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 19, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Brian M. Erwin, Eric D. Perfecto, Wolfgang Sauter, Thomas A. Wassick
  • Patent number: 9190376
    Abstract: The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: November 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Brian M. Erwin, Eric D. Perfecto, Wolfgang Sauter, Thomas A. Wassick