Patents by Inventor Thomas A. Wassick
Thomas A. Wassick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8298929Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.Type: GrantFiled: December 3, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Gary Lafontant, Ekta Misra, David L. Questad, George J. Scott, Krystyna W. Semkow, Timothy D. Sullivan, Thomas A. Wassick, Steven L. Wright
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Publication number: 20120139123Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Daubenspeck, Gary Lafontant, Ekta Misra, David L. Questad, George J. Scott, Krystyna W. Semkow, Timothy D. Sullivan, Thomas A. Wassick, Steven L. Wright
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Publication number: 20110147922Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raschid J. BEZAMA, Timothy H. DAUBENSPECK, Gary LaFONTANT, Ian D. MELVILLE, Ekta MISRA, George J. SCOTT, Krystyna W. SEMKOW, Timothy D. SULLIVAN, Robin A. SUSKO, Thomas A. WASSICK, Xiaojin WEI, Steven L. WRIGHT
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Patent number: 7716992Abstract: The invention generally relates to a design structure of a circuit design, and more particularly to a design structure of a delamination sensor for use with low-k materials. A delamination sensor includes at least one first sensor formed in a layered semiconductor structure and a second sensor formed in the layered semiconductor structure. The at least one first sensor is structured and arranged to detect a defect, and the second sensor is structured and arranged to identify an interface where the defect exists.Type: GrantFiled: March 27, 2008Date of Patent: May 18, 2010Assignee: International Business Machines CorporationInventors: John J. Maloney, Wolfgang Sauter, Thomas A. Wassick, Jeffrey S. Zimmerman
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Publication number: 20090246892Abstract: The invention generally relates to a design structure of a circuit design, and more particularly to a design structure of a delamination sensor for use with low-k materials. A delamination sensor includes at least one first sensor formed in a layered semiconductor structure and a second sensor formed in the layered semiconductor structure. The at least one first sensor is structured and arranged to detect a defect, and the second sensor is structured and arranged to identify an interface where the defect exists.Type: ApplicationFiled: March 27, 2008Publication date: October 1, 2009Inventors: John J. Maloney, Wolfgang Sauter, Thomas A. Wassick, Jeffrey S. Zimmerman
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Patent number: 7294909Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.Type: GrantFiled: April 5, 2005Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Jon A. Casey, James G. Balz, Michael Berger, Jerome Cohen, Charles Hendricks, Richard Indyk, Mark LaPlante, David C. Long, Lori A. Maiorino, Arthur G. Merryman, Glenn A. Pomerantz, Robert A. Rita, Krystyna W. Semkow, Patrick E. Spencer, Brian R. Sundlof, Richard P. Surprenant, Donald R. Wall, Thomas A. Wassick, Kathleen M. Wiley
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Publication number: 20050176255Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.Type: ApplicationFiled: April 5, 2005Publication date: August 11, 2005Inventors: Jon Casey, James Balz, Michael Berger, Jerome Cohen, Charles Hendricks, Richard Indyk, Mark LaPlante, David Long, Lori Maiorino, Arthur Merryman, Glenn Pomerantz, Robert Rita, Krystyna Semkow, Patrick Spencer, Brian Sundlof, Richard Surprenant, Donald Wall, Thomas Wassick, Kathleen Wiley
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Patent number: 6916670Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.Type: GrantFiled: February 4, 2003Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: Jon A. Casey, James G. Balz, Michael Berger, Jerome Cohen, Charles Hendricks, Richard Indyk, Mark LaPlante, David C. Long, Lori A. Maiorino, Arthur G. Merryman, Glenn A. Pomerantz, Robert A. Rita, Krystyna W. Semkow, Patrick E. Spencer, Brian R. Sundlof, Richard P. Surprenant, Donald R. Wall, Thomas A. Wassick, Kathleen M. Wiley
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Publication number: 20050082676Abstract: This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.Type: ApplicationFiled: October 17, 2003Publication date: April 21, 2005Applicant: International Business Machines CorporationInventors: Paul Andry, Leena Buchwalter, Russell Budd, Thomas Wassick
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Patent number: 6823585Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.Type: GrantFiled: March 28, 2003Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: Mark J. LaPlante, Jon A. Casey, Thomas A. Wassick, David C. Long, Krystyna W. Semkow, Patrick E. Spencer, Robert A. Rita, Richard F. Indyk, Kathleen M. Wiley, Brian R. Sundlof, James Balz, Lori A. Maiorino, Donald R. Wall, Glenn A. Pomerantz
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Publication number: 20040187303Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.Type: ApplicationFiled: March 28, 2003Publication date: September 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark J. LaPlante, Jon A. Casey, Thomas A. Wassick, David C. Long, Krystyna W. Semkow, Patrick E. Spencer, Robert A. Rita, Richard F. Indyk, Kathleen M. Wiley, Brian R. Sundlof, James Balz, Lori A. Maiorino, Donald R. Wall, Glenn A. Pomerantz
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Publication number: 20040148765Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.Type: ApplicationFiled: February 4, 2003Publication date: August 5, 2004Applicant: International Business Machines CorporationInventors: Jon A. Casey, James G. Balz, Michael Berger, Jerome Cohen, Charles Hendricks, Richard Indyk, Mark LaPlante, David C. Long, Lori A. Maiorino, Arthur G. Merryman, Glenn A. Pomerantz, Robert A. Rita, Krystyna W. Semkow, Patrick E. Spencer, Brian R. Sundlof, Richard P. Surprenant, Donald R. Wall, Thomas A. Wassick, Kathleen M. Wiley
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Patent number: 6682872Abstract: Radiation-curable compositions are provided for use in the fabrication of electronic components as passivation coatings; for defect repair in ceramic and thin film products by micropassivation in high circuit density electronic modules to allow product recovery; as a solder mask in electronic assembly processes; for use as protective coatings on printed circuit board (PCB) circuitry and electronic devices against mechanical damage and corrosion from exposure to the environment. The compositions are solvent-free, radiation-curable, preferably uv-curable, containing a polymer binder, which is a pre-formed thermoplastic or elastomeric polymer/oligomer, a monofunctional and/or bifunctional acrylic monomer, a multifunctional (more than 2 reactive groups) acrylated/methacrylated monomer, and a photoinitiator, where all the constituents are mutually miscible forming a homogeneous viscous blend without the addition of an organic solvent. The compositions may also contain inorganic fillers and/or nanoparticle fillers.Type: GrantFiled: January 22, 2002Date of Patent: January 27, 2004Assignee: International Business Machines CorporationInventors: Krishna G. Sachdev, Michael Berger, Rebecca Y. Gorrell, Gregg B. Monjeau, Bernadette H. Perry, Thomas A. Wassick
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Publication number: 20030138733Abstract: Radiation-curable compositions are provided for use in the fabrication of electronic components as passivation coatings; for defect repair in ceramic and thin film products by micropassivation in high circuit density electronic modules to allow product recovery; as a solder mask in electronic assembly processes; for use as protective coatings on printed circuit board (PCB) circuitry and electronic devices against mechanical damage and corrosion from exposure to the environment. The compositions are solvent-free, radiation-curable, preferably uv-curable, containing a polymer binder, which is a pre-formed thermoplastic or elastomeric polymer/oligomer, a monofunctional and/or bifunctional acrylic monomer, a multifunctional (more than 2 reactive groups) acrylated/methacrylated monomer, and a photoinitiator, where all the constituents are mutually miscible forming a homogeneous viscous blend without the addition of an organic solvent. The compositions may also contain inorganic fillers and/or nanoparticle fillers.Type: ApplicationFiled: January 22, 2002Publication date: July 24, 2003Applicant: International Business Machines CorporationInventors: Krishna G. Sachdev, Michael Berger, Rebecca Y. Gorrell, Gregg B. Monjeau, Bernadette H. Perry, Thomas A. Wassick
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Patent number: 6541709Abstract: A multilayer thin film structure having defined strap repair lines thereon and a method for repairing interconnections in the multilayer thin film structure (MLTF) and/or making engineering changes (EC) are provided. The method determines interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, defines the top surface metallization including a series of orthogonal X conductor lines and Y conductor lines using photoresist and lithography and additive or subtractive metallization techniques and then uses a phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make EC's, and forms the top surface metallization.Type: GrantFiled: November 1, 1996Date of Patent: April 1, 2003Assignee: International Business Machines CorporationInventors: Peter A. Franklin, Arthur G. Merryman, Rajesh S. Patel, Thomas A. Wassick
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Patent number: 6455331Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.Type: GrantFiled: May 29, 2001Date of Patent: September 24, 2002Assignee: International Business Machines CorporationInventors: Roy Yu, Kamalesh S. Desai, Peter A. Franklin, Suryanarayana Kaja, Kimberley A. Kelly, Yeeling L. Lee, Arthur G. Merryman, Frank R. Morelli, Thomas A. Wassick
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Patent number: 6427324Abstract: A multilayer thin film structure having defined strap repair lines thereon and a method for repairing interconnections in the multilayer thin film structure (MLTF) and/or making engineering changes (EC) are provided. The method comprises determining interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, defining the top surface metallization including a series of orthogonal X conductor lines and Y conductor lines using photoresist and lithography and additive or phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization.Type: GrantFiled: July 13, 1998Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Peter A. Franklin, Arthur G. Merryman, Rajesh S. Patel, Thomas A. Wassick
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Patent number: 6323045Abstract: A method and structure for providing top-to-bottom repair of a defective I/O net in a thin film transfer and join process. At least one C4 location and at least one capture pad are provided on a thin film substrate. The substrate is preferably ceramic. The C4 location of the defective net is severed by removal of a delete strap. The corresponding solder connection of the associated capture pad is also removed. A spare C4 location and capture pad are connected to provide a Z-repair line imbedded in the TF wiring structure. The Z-repair line is wired to the defective net.Type: GrantFiled: December 8, 1999Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Christopher Cline, Nancy W. Hannon, Chandrika Prasad, Thomas A. Wassick, Roy Yu
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Publication number: 20010023081Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.Type: ApplicationFiled: May 29, 2001Publication date: September 20, 2001Inventors: Roy Yu, Kamalesh S. Desal, Peter A. Franklin, Suryanatayana Kala, Kimberley A. Kelly, Yeeling L. Lee, Arthur G. Merryman, Frank R. Morelll, Thomas A. Wassick
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Patent number: 6248599Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.Type: GrantFiled: December 2, 1999Date of Patent: June 19, 2001Assignee: International Business Machines CorporationInventors: Roy Yu, Kamalesh S. Desai, Peter A. Franklin, Suryanarayana Kaja, Kimberley A. Kelly, Yeeling L. Lee, Arthur G. Merryman, Frank R. Morelli, Thomas A. Wassick