Abstract: An integrated memory includes a cell array having memory cells disposed at points of intersection of first bit lines and second bit lines with word lines in the cell array. When one of the memory cells is addressed, the memory content is not affected if respective bit lines associated with each of the memory cells are at a standby potential. Sense amplifiers for amplifying data read from the memory cells onto the bit lines are included, each associated with respective first and second bit lines and disposed on opposite sides of the cell array. Also provided are first switching elements, through which each bit line is connected to the associated sense amplifier, and second switching elements, through which each bit line is connected, on that side of its first switching element which is remote from the associated sense amplifier, to a standby potential.

Abstract: The memory cell configuration has a multiplicity of preferably ferroelectric memory cells in a semiconductor substrate. Mutually parallel bit line trenches run in the longitudinal direction in the main surface of the semiconductor substrate. Bit lines are disposed in the bottoms of the trenches. Source/drain regions are formed in the crowns of the trenches. Channel regions are provided in the walls of the trenches. The channel region on a wall in each case is configured such that a drivable selection transistor of the relevant memory cell is formed there, while the channel region on the other wall is configured such that the transistor located there is closed. Insulated word lines for driving the selection transistors run in the transverse direction along the main surface of the semiconductor substrate through the bit line trenches.

Abstract: An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.

Abstract: An arrangement for and a method of reading bar code symbols on a target to move a light beam emitted by a light source in a multiple line, scan pattern during a scan period in a first operational mode. Upon selection of a second operational mode by a user, a controller intermittently operates and energizes the light source to emit the light beam for a working time period which is less than, and a fraction of, the scan period to generate a single scan line across the symbol.

Abstract: An integrated memory having a first wiring plane with parallel conductor tracks running therein. A second wiring plane in the memory has segments running in it that are parallel to the conductor tracks. Word lines are each formed by a conductor track of a first type and by segments configured parallel to this conductor track. A conductor track of a second type is connected to a first supply line and to regions that are configured in a third wiring plane within the cell array.

Abstract: The invention relates to a process for preparing clonogenic fibroblasts, with tissue being removed from the donor and the individual cells being isolated from the tissue, the resulting cell suspension being strained, the cells which are contained in the cell suspension being washed and the cells being converted into a tissue culture, with the exception of the isolation of individual cells by mechanical comminution, followed by an enzymic treatment with collagenase alone, and with at least one gene being inserted into the fibroblasts by means of the transfection, which gene encodes a biologically active protein, preferably a therapeutically active protein, for example a growth factor, a hormone, an enzyme, a coagulation factor or a coagulation inhibitor.

Abstract: A system for processing output signals of an electro-optical scanner adapted for reading a bar code indicia having parts of different light reflectivity and non bar code indicia adjacent the bar code on an article being scanned comprises a decoder for decoding content of signals input thereto and signal processing circuitry for receiving the scanner output signals and generating input signals for input to the decoder by deleting signals having non bar code indicia content from the received scanner output signals by examining characteristics of the received scanner output signals. The signal processing circuitry is adapted to generate input signals for input to the decoder for bar code indicia of respective different bar code symbologies. The signal processing circuitry includes deletion circuitry for deleting, from the received scanner output signals, signals having less time duration than a predetermined time duration.