Patents by Inventor Thomas Bert Gorczyca

Thomas Bert Gorczyca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10276486
    Abstract: A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 30, 2019
    Assignee: General Electric Company
    Inventors: Thomas Bert Gorczyca, Richard Joseph Saia, Paul Alan McConnelee
  • Patent number: 9929319
    Abstract: A process for fabricating a LED lighting apparatus includes disposing a composite coating on a surface of a LED chip. The composite coating comprises a first composite layer having a manganese doped phosphor of formula I and a first binder, and a second composite layer comprising a second phosphor composition and a second binder. The first binder, the second binder or both include a poly(meth)acrylate. Ax[MFy]:Mn4+??(I) wherein A is Li, Na, K, Rb, Cs, or a combination thereof; M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Hf, Y, La, Nb, Ta, Bi, Gd, or a combination thereof; x is the absolute value of the charge of the [MFy] ion; y is 5, 6 or 7.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 27, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Anant Achyut Setlur, Stanton Earl Weaver, Thomas Bert Gorczyca, Ashfaqul Islam Chowdhury, James Edward Murphy, Florencio Garcia
  • Publication number: 20170236915
    Abstract: In an embodiment, a wide bandgap semiconductor power device, includes a wide bandgap semiconductor substrate layer; an epitaxial semiconductor layer disposed above the wide bandgap semiconductor substrate layer; a gate dielectric layer disposed directly over a portion of the epitaxial semiconductor layer; and a gate electrode disposed directly over the gate dielectric layer. The gate electrode includes an in-situ doped semiconductor layer disposed directly over the gate dielectric layer and a metal-containing layer disposed directly over the in-situ doped semiconductor layer.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Inventor: Thomas Bert Gorczyca
  • Publication number: 20150364659
    Abstract: A process for fabricating a LED lighting apparatus includes disposing a composite coating on a surface of a LED chip. The composite coating comprises a first composite layer having a manganese doped phosphor of formula I and a first binder, and a second composite layer comprising a second phosphor composition and a second binder. The first binder, the second binder or both include a poly(meth)acrylate. Ax[MFy]:Mn4+??(I) wherein A is Li, Na, K, Rb, Cs, or a combination thereof; M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Hf, Y, La, Nb, Ta, Bi, Gd, or a combination thereof; x is the absolute value of the charge of the [MFy] ion; y is 5, 6 or 7.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: Anant Achyut Setlur, Stanton Earl Weaver, Thomas Bert Gorczyca, Ashfaqul Islam Chowdhury, James Edward Murphy, Florencio Garcia
  • Publication number: 20150236151
    Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: James Jay McMahon, Ljubisa Dragoljub Stevanovic, Stephen Daley Arthur, Thomas Bert Gorczyca, Richard Alfred Beaupre, Zachary Matthew Stum, Alexander Viktorovich Bolotnikov
  • Patent number: 8704211
    Abstract: A composite article with at least one high integrity protective coating, the high integrity protective coating having at least one planarizing layer and at least one organic-inorganic composition barrier coating layer. A method for depositing a high integrity protective coating.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: April 22, 2014
    Assignee: General Electric Company
    Inventors: Tae Won Kim, Min Yan, Christian Maria Anton Heller, Marc Schaepkens, Thomas Bert Gorczyca, Paul Alan McConnelee, Ahmet Gun Erlat
  • Patent number: 8691371
    Abstract: A barrier coating for a composite article is provided. The barrier coating includes an organic zone; an inorganic zone; and an interface zone between the organic zone and the inorganic zone.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: April 8, 2014
    Assignee: General Electric Company
    Inventors: Tae Won Kim, Min Yan, Ahmet Gun Erlat, Thomas Bert Gorczyca, Christian Maria Anton Heller, Paul Alan McConnelee, Marc Schaepkens
  • Patent number: 8629003
    Abstract: An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: January 14, 2014
    Assignee: General Electric Company
    Inventors: Thomas Bert Gorczyca, Paul Alan McConnelee
  • Patent number: 8604612
    Abstract: Present embodiments are directed to an adhesive and method for assembling a chip package. The adhesive may be used to couple a chip to a substrate, and the adhesive may include an epoxy-based dielectric material, an epoxy resin, a photoacid generator, an antioxidant, and a cold catalyst corresponding to the photoacid generator.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: December 10, 2013
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Thomas Bert Gorczyca
  • Patent number: 8586421
    Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 19, 2013
    Assignee: General Electric Company
    Inventors: Richard Alfred Beaupre, Paul Alan McConnelee, Arun Virupaksha Gowda, Thomas Bert Gorczyca
  • Patent number: 8431444
    Abstract: An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 30, 2013
    Assignee: General Electric Company
    Inventors: Thomas Bert Gorczyca, Paul Alan McConnelee
  • Patent number: 8427845
    Abstract: Packaged optoelectronic device include a first barrier layer having a plurality of feedthrough apertures communicating with at least one electrode layer of the device, and a plurality of conductive patches disposed on at least one of the plurality of feedthrough apertures for electrically connecting the device to a power supply. Each conductive patch includes a conductive metal surface layer and a non-conducting surface layer having an opening exposing the metal surface layer.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: April 23, 2013
    Assignee: General Electric Company
    Inventors: Thomas Bert Gorczyca, Stefan Rakuff, Michael Scott Herzog
  • Publication number: 20130045575
    Abstract: An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 21, 2013
    Inventors: Thomas Bert Gorczyca, Paul Alan McConnelee
  • Publication number: 20120329207
    Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.
    Type: Application
    Filed: September 7, 2012
    Publication date: December 27, 2012
    Inventors: Richard Alfred Beaupre, Paul Alan McConnelee, Arun Virupaksha Gowda, Thomas Bert Gorczyca
  • Patent number: 8310040
    Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: November 13, 2012
    Assignee: General Electric Company
    Inventors: Richard Alfred Beaupre, Paul Alan McConnelee, Arun Virupaksha Gowda, Thomas Bert Gorczyca
  • Publication number: 20120222721
    Abstract: A photovoltaic module package and fabrication method. The module includes photovoltaic cells, a dielectric material, and metallized material. Each photovoltaic cells includes a substrate material having a sun side and a backside, first doped regions interdigitated with second doped regions, both doped regions being located on the backside, and one being positively doped and the being negatively doped, and electrical contacts on each of the first and second doped regions. The dielectric material is adhered to the backside of the substrate material. Vias are formed through the dielectric material, extending to at least a portion of the electrical contacts. The metallized material extends from the electrical contacts through the vias and are patterned on a backside of the dielectric material. The metallized material is formed of a material that is both electrically and thermally conductive.
    Type: Application
    Filed: March 2, 2011
    Publication date: September 6, 2012
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Thomas Bert Gorczyca, Charles Steven Korman, Scott Smith
  • Publication number: 20120146234
    Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.
    Type: Application
    Filed: December 8, 2010
    Publication date: June 14, 2012
    Inventors: Richard Alfred Beaupre, Paul Alan McConnelee, Arun Virupaksha Gowda, Thomas Bert Gorczyca
  • Publication number: 20110215480
    Abstract: A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 8, 2011
    Inventors: Thomas Bert Gorczyca, Richard Joseph Saia, Paul Alan McConnelee
  • Patent number: 7956457
    Abstract: An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: June 7, 2011
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kevin M. Durocher, Elizabeth A. Burke, Thomas Bert Gorczyca, Charles G. Woychik
  • Publication number: 20100296261
    Abstract: Packaged optoelectronic device include a first barrier layer having a plurality of feedthrough apertures communicating with at least one electrode layer of the device, and a plurality of conductive patches disposed on at least one of the plurality of feedthrough apertures for electrically connecting the device to a power supply. Each conductive patch includes a conductive metal surface layer and a non-conducting surface layer having an opening exposing the metal surface layer.
    Type: Application
    Filed: May 26, 2010
    Publication date: November 25, 2010
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Thomas Bert Gorczyca, Stefan Rakuff, Michael Scott Herzog