Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.

Abstract: A method for molding an optical disk comprises: applying a thermally insulative insert coating to at least one thermally insulative mold insert to provide at least one coated mold insert having a reduced surface roughness; positioning the coated mold insert between a thermally conductive mold form and a portion of a thermally conductive mold apparatus; injecting a molten thermoplastic material into the mold apparatus; retaining the material in the mold apparatus for a time sufficient for the molten thermoplastic material to cool below its glass transition temperature to form the optical disk; and ejecting the optical disk from the mold apparatus. In another embodiment, the mold insert is coated or laminated on the mold form with the mold insert having a coefficient of thermal expansion compatible with the coefficient of thermal expansion of the mold form. In another embodiment, the mold insert is fabricated by being applied, cured, and then removed from a release layer.

Abstract: A thermal processor for at least one semiconductor wafer includes a reactor chamber having a material substantially transparent to light including a wavelength within the range of about 200 nanometers to about 800 nanometers for holding the at least one semiconductor wafer. A coating including a material substantially reflective of infrared radiation can be present on at least a portion of the reactor chamber. A light source provides radiant energy to the at least one semiconductor wafer through the coating and the reactor chamber. The light source can include an ultraviolet discharge lamp, a halogen infrared incandescent lamp, or a metal halide visible discharge lamp. The coating can be situated on an inner or outer surface of the reactor chamber. If the reactor chamber has inner and outer walls, the coating can be situated on either the inner wall or the outer wall.

Abstract: A protective cap is deposited over the top and sides of an air bridge structure located on an integrated circuit chip. The protective cap provides mechanical strength during the application of a high density interconnect structure over the chips, to prevent deformation of the sensitive (air bridge) structure, and also to prevent any contamination from intruding under the air bridge. More importantly, the protective cap does not impede the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure. Furthermore, the protective cap allows additional area for metallization to provide alternate circuits for coupling, power or ground planes, etc.

Abstract: First and second flexible interconnect structures are provided and each includes a flexible interconnect layer and a chip with a surface having chip pads attached to the flexible interconnect layer. Molding material is inserted between the flexible interconnect layers for encapsulating the respective chips. Vias in the flexible interconnect layers are formed to extend to selected chip pads, and a pattern of electrical conductors is applied which extends over the flexible interconnect layers and into the vias to couple selected ones of the chip pads.