Patents by Inventor Thomas Bertrams

Thomas Bertrams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9166039
    Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: October 20, 2015
    Assignee: Infineon Technologies AG
    Inventors: Erhard Landgraf, Thomas Bertrams, Claus Dahl, Henning Feick, Andreas Pribil
  • Publication number: 20150294966
    Abstract: A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes a first isolation layer on the first surface of the semiconductor body and a first electrostatic discharge protection structure on the first isolation layer. The first electrostatic discharge protection structure has a first terminal and a second terminal. A second isolation layer is provided on the electrostatic discharge protection structure. A gate contact area on the second isolation layer is electrically coupled to the first terminal of the first electrostatic discharge protection structure. An electric contact structure is arranged in an overlap area between the gate contact area and the semiconductor body. The electric contact structure is electrically coupled to the second terminal of the first electrostatic discharge protection structure and electrically isolated from the gate contact area.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 15, 2015
    Inventors: Joachim Weyers, Franz Hirler, Anton Mauder, Markus Schmitt, Armin Tilke, Thomas Bertrams
  • Patent number: 9076666
    Abstract: Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semi-conductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: July 7, 2015
    Assignees: SOITEC, Arizona Board of Regents For and On Behalf Arizona State University
    Inventors: Chantal Arena, Ronald Thomas Bertram, Jr., Ed Lindow, Subhash Mahajan, Ilsu Han
  • Publication number: 20150167161
    Abstract: A gas injector includes a base plate, a middle plate, and a top plate. The base plate, middle plate, and top plate are configured to flow a purge gas between the base plate and the middle plate and to flow a precursor gas between the middle plate and the top plate. Another gas injector includes a precursor gas inlet, a lateral precursor gas flow channel, and a plurality of precursor gas flow channels. The plurality of precursor gas flow channels extend from the at least one lateral precursor gas flow channel to an outlet of the gas injector. Methods of forming a material on a substrate include flowing a precursor between a middle plate and a top plate of a gas injector and flowing a purge gas between a base plate and the middle plate of the gas injector.
    Type: Application
    Filed: May 24, 2013
    Publication date: June 18, 2015
    Applicant: Soitec
    Inventors: Claudio Canizares, Dan Gura, Ronald Thomas Bertram, JR.
  • Patent number: 9023721
    Abstract: Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 5, 2015
    Assignee: Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, Ed Lindow
  • Publication number: 20150099065
    Abstract: Visor injectors include a gas injector port, internal sidewalls, and at least two ridges for directing gas flow through the visor injectors. Each of the ridges extends from a location proximate a hole in the gas injector port toward a gas outlet of the visor injector and is positioned between the internal sidewalls. Deposition systems include a base with divergently extending internal sidewalls, a gas injection port, a lid, and at least two divergently extending ridges for directing gas flow through a central region of a space at least partially defined by the internal sidewalls of the base and a bottom surface of the lid. Methods of forming a material on a substrate include flowing a precursor through such a visor injector and directing a portion of the precursor to flow through a central region of the visor injector with at least two ridges.
    Type: Application
    Filed: May 24, 2013
    Publication date: April 9, 2015
    Inventors: Claudio Canizares, Ronald Thomas Bertram, Jr.
  • Publication number: 20150063978
    Abstract: A vertical axis wind turbine system is provided that converts wind energy into electrical or mechanical energy. The turbine comprises at least one turbine rotor with a plurality of curved blades for receiving head-on wind generated airflow. Shield means mountable around at least a portion of the rotor serve to protect the upstream-moving blades from head-on wind airflow and thereby reduce drag. In one embodiment, load compensation means are provided to adjust the moment of inertia of the turbine rotor. One or more of the turbine rotor blades is hollow and defines a closed volume for holding a fluid, the fluid being displaceable in use through baffle means towards or away from the vertical axis of the rotor as the rotational velocity of the rotor changes.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 5, 2015
    Inventor: Thomas Bertram Poole
  • Publication number: 20140339634
    Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.
    Type: Application
    Filed: July 1, 2014
    Publication date: November 20, 2014
    Inventors: Erhard Landgraf, Thomas Bertrams, Claus Dahl, Henning Feick, Andreas Pribil
  • Publication number: 20140305203
    Abstract: The invention relates inter alia to a sensor (10), in particular for triggering a vehicle security device (1). According to the invention the senor (10)comprises a support element(40)and a housing part (70), which holds the support element(40), and the housing part (70)consists of a softer material than the support element (40).
    Type: Application
    Filed: November 7, 2012
    Publication date: October 16, 2014
    Applicant: Takata AG
    Inventors: Peter Baumgartner, Hermann Hasse, Oswald Lustig, Thomas Bertram
  • Patent number: 8809952
    Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: August 19, 2014
    Assignee: Infineon Technologies AG
    Inventors: Erhard Landgraf, Thomas Bertrams, Claus Dahl, Henning Feick, Andreas Pribil
  • Publication number: 20140217553
    Abstract: Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.
    Type: Application
    Filed: November 23, 2011
    Publication date: August 7, 2014
    Applicants: ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY, Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, JR., Ed Lindow, Subhash Mahajan, Ilsu Han
  • Patent number: 8741385
    Abstract: The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: June 3, 2014
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan J. Werkhoven, Ronald Thomas Bertram, Jr., Ed Lindow
  • Patent number: 8574968
    Abstract: This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: November 5, 2013
    Assignees: Soitec, Arizona Board of Regents for and on Behalf of Arizona State University
    Inventors: Chantal Arena, Christiaan J. Werkhoven, Ronald Thomas Bertram, Jr., Ed Lindow, Subhash Mahajan, Ranjan Datta, Rahul Ajay Trivedi, Ilsu Han
  • Publication number: 20130280892
    Abstract: Methods of depositing material on a substrate include forming a precursor gas and a byproduct from a source gas within a thermalizing gas injector. The byproduct may be reacted with a liquid reagent to form additional precursor gas, which may be injected from the thermalizing gas injector into a reaction chamber. Thermalizing gas injectors for injecting gas into a reaction chamber of a deposition system may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. A pathway may extend from the inlet, through the thermalizing conduit to an interior space within the liquid container, and from the interior space within the liquid container to the outlet. The thermalizing conduit may have a length that is greater than a shortest distance between the inlet and the liquid container. Deposition systems may include one or more such thermalizing gas injectors.
    Type: Application
    Filed: June 17, 2013
    Publication date: October 24, 2013
    Inventor: Ronald Thomas Bertram, JR.
  • Publication number: 20130244410
    Abstract: Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process.
    Type: Application
    Filed: November 23, 2011
    Publication date: September 19, 2013
    Applicant: Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, Ed Lindow
  • Publication number: 20130234157
    Abstract: Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer.
    Type: Application
    Filed: November 23, 2011
    Publication date: September 12, 2013
    Applicant: Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, JR., Ed Lindow, Subhash Mahajan, Fanyu Meng
  • Publication number: 20130195636
    Abstract: A vertical axis wind turbine system is provided that converts wind enemy into electrical or mechanical enemy. The turbine comprises at least one turbine rotor with a plurality of curved blades for receiving head-on wind generated airflow. Shield means mountable around at least a portion of the rotor serve to protect the upstream-moving blades from head-on wind airflow and thereby reduce drag. In one embodiment, load compensation means are provided to adjust the moment of inertia of the turbine rotor. One or more of the turbine rotor blades is hollow and defines a closed volume for holding a fluid, the fluid being displaceable in use through baffle means towards or away from the vertical axis of the rotor as the rotational velocity of the rotor changes.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Inventor: Thomas Bertram Poole
  • Patent number: 8486192
    Abstract: Methods of depositing material on a substrate include forming a precursor gas and a byproduct from a source gas within a thermalizing gas injector. The byproduct may be reacted with a liquid reagent to form additional precursor gas, which may be injected from the thermalizing gas injector into a reaction chamber. Thermalizing gas injectors for injecting gas into a reaction chamber of a deposition system may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. A pathway may extend from the inlet, through the thermalizing conduit to an interior space within the liquid container, and from the interior space within the liquid container to the outlet. The thermalizing conduit may have a length that is greater than a shortest distance between the inlet and the liquid container. Deposition systems may include one or more such thermalizing gas injectors.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: July 16, 2013
    Assignee: Soitec
    Inventor: Ronald Thomas Bertram, Jr.
  • Publication number: 20130160802
    Abstract: Processes and systems are used to reduce undesired deposits within a reaction chamber associated with a semiconductor deposition system. A cleaning gas may be caused to flow through at least one gas flow path extending through at least one gas furnace, and the heated cleaning gas may be introduced into a reaction chamber to remove at least a portion of undesired deposits from within the reaction chamber.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 27, 2013
    Applicant: Soitec
    Inventor: Ronald Thomas Bertram, JR.
  • Patent number: 8455370
    Abstract: This invention provides methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a method for moving wafers or substrates that can bathe a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: June 4, 2013
    Assignee: Soitec
    Inventors: Michael Albert Tischler, Ronald Thomas Bertram, Jr.