Patents by Inventor Thomas Boesch
Thomas Boesch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977971Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.Type: GrantFiled: February 10, 2023Date of Patent: May 7, 2024Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.r.lInventors: Surinder Pal Singh, Thomas Boesch, Giuseppe Desoli
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Publication number: 20240076092Abstract: The invention relates to a container produced from a plastic material, in particular by extrusion blow molding, said container comprising a container body having a first end and a second end substantially opposite the first end and having a jacket; a filling opening having a first and second sealing surface formed on the inner wall of the first end, wherein the first and second sealing surfaces can be connected to one another in a fluid-tight manner; and a container base having a standing surface formed at the second end and a pouring opening formed at the first end. The filling opening has a first center axis, and the pouring opening has a second center axis. The first and the second center axis are substantially parallel to one another.Type: ApplicationFiled: January 21, 2022Publication date: March 7, 2024Inventors: Oliver Unterlechner, Florian Heider, Klemens Bösch, Thomas Bohle
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Patent number: 11900240Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.Type: GrantFiled: September 16, 2020Date of Patent: February 13, 2024Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Giuseppe Desoli, Manuj Ayodhyawasi, Thomas Boesch, Surinder Pal Singh
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Publication number: 20240045589Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin CHAWLA, Giuseppe DESOLI, Anuj GROVER, Thomas BOESCH, Surinder Pal SINGH, Manuj AYODHYAWASI
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Patent number: 11880759Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.Type: GrantFiled: February 22, 2023Date of Patent: January 23, 2024Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Giuseppe Desoli, Carmine Cappetta, Thomas Boesch, Surinder Pal Singh, Saumya Suneja
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Publication number: 20240012871Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and iteration control circuitry. The convolutional accelerator, in operation, convolves a kernel with a streaming feature data tensor. The convolving includes decomposing the kernel into a plurality of sub-kernels and iteratively convolving the sub-kernels with respective sub-tensors of the streamed feature data tensor. The iteration control circuitry, in operation, defines respective windows of the streamed feature data tensors, the windows corresponding to the sub-tensors.Type: ApplicationFiled: July 7, 2022Publication date: January 11, 2024Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Antonio DE VITA, Thomas BOESCH, Giuseppe DESOLI
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Publication number: 20230418559Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Michele ROSSI, Thomas BOESCH, Giuseppe DESOLI
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Patent number: 11836346Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: GrantFiled: May 12, 2022Date of Patent: December 5, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Pal Singh, Manuj Ayodhyawasi
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Patent number: 11836608Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.Type: GrantFiled: November 18, 2022Date of Patent: December 5, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Thomas Boesch, Giuseppe Desoli, Surinder Pal Singh, Carmine Cappetta
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Patent number: 11823771Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.Type: GrantFiled: January 26, 2021Date of Patent: November 21, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Thomas Boesch, Anuj Grover, Surinder Pal Singh, Giuseppe Desoli
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Publication number: 20230350483Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.Type: ApplicationFiled: June 21, 2023Publication date: November 2, 2023Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin CHAWLA, Anuj GROVER, Giuseppe DESOLI, Kedar Janardan DHORI, Thomas BOESCH, Promod KUMAR
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Patent number: 11754827Abstract: An apparatus for inserting a measurement light beam which can be projected onto a target object, comprising a light-refracting component having an optical axis, and at least two mirrors for deflecting the measurement light beam, and an optical overall body consisting of at least one optically effective material, wherein the optical overall body is configured in such a way that the at least two mirrors are fitted inside or at the edge, in particular as a part, of the optical overall body, in such a way that the measurement light beam entering the optical overall body is offset parallel to the incident measurement light beam when emerging from the optical overall body, so that the emerging measurement light beam lies on the optical axis of the light-refracting component of the apparatus and is projected in this form onto the target object.Type: GrantFiled: December 11, 2020Date of Patent: September 12, 2023Assignee: LEICA GEOSYSTEMS AGInventors: Thomas Bösch, Josef Müller
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Patent number: 11740870Abstract: A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.Type: GrantFiled: March 27, 2020Date of Patent: August 29, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Giuseppe Desoli, Thomas Boesch, Carmine Cappetta, Ugo Maria Iannuzzi
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Patent number: 11726543Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.Type: GrantFiled: December 3, 2020Date of Patent: August 15, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar
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Patent number: 11710032Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.Type: GrantFiled: November 14, 2022Date of Patent: July 25, 2023Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.Inventors: Surinder Pal Singh, Thomas Boesch, Giuseppe Desoli
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Publication number: 20230206032Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.Type: ApplicationFiled: February 22, 2023Publication date: June 29, 2023Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Giuseppe DESOLI, Carmine CAPPETTA, Thomas BOESCH, Surinder Pal SINGH, Saumya SUNEJA
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Patent number: 11687762Abstract: Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.Type: GrantFiled: February 20, 2019Date of Patent: June 27, 2023Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Surinder Pal Singh, Thomas Boesch, Giuseppe Desoli
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Publication number: 20230186067Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Surinder Pal SINGH, Thomas BOESCH, Giuseppe DESOLI
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Patent number: 11675943Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.Type: GrantFiled: November 10, 2020Date of Patent: June 13, 2023Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Thomas Boesch, Giuseppe Desoli
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Publication number: 20230153621Abstract: An integrated circuit includes a reconfigurable stream switch and an arithmetic circuit. The stream switch, in operation, streams data. The arithmetic circuit has a plurality of inputs coupled to the reconfigurable stream switch. In operation, the arithmetic circuit generates an output according to AX+BY+C, where A, B and C are vector or scalar constants, and X and Y are data streams streamed to the arithmetic circuit through the reconfigurable stream switch.Type: ApplicationFiled: January 19, 2023Publication date: May 18, 2023Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Surinder Pal SINGH, Giuseppe DESOLI, Thomas BOESCH