Abstract: A hardware accelerator includes a stream switch, a programmable component and multi-context control circuitry. The stream switch streams a data stream to the programmable component and to the multi-context control circuitry. The multi-context control circuitry, in a configured context mode of operation, counts valid data transactions of the data stream streamed to the programmable component, and controls a sequence of processing operations to be performed on the data of the data stream by the programmable component based on the counting of the valid data transactions of the data stream and on stored configured-context mode configuration information. The multi-context control circuitry, in a hybrid context mode of operation, monitors the data stream to read embedded context tags, and controls a sequence of processing operations to be performed on the data based on the embedded context tags, on the counting of the valid data transactions, and stored hybrid-context mode configuration information.

Abstract: A stream-triggered multi-thread accelerator includes a data streaming interface, a memory, vector processing circuitry and scheduling circuitry. The data streaming interface, in operation, receives and transmits data streams of a plurality of data streaming channels. The memory, in operation, stores a plurality of instruction threads. The plurality of instruction threads include wait-for-trigger instructions specifying streaming data trigger thresholds, and instructions having data streaming channels of the plurality of data streaming channels as operands. The vector processing circuitry is coupled to the memory and to the data streaming interface. The vector processing circuitry, in operation, executes instruction threads of the plurality of instruction threads. The scheduling circuitry, in operation, schedules execution of instruction threads of the plurality of instruction threads by the vector processing circuitry based on the streaming data trigger thresholds of the wait-for-trigger instructions.

Abstract: A neural processing unit implements a neural network and includes a decompression unit including a plurality of decompression cores. During operation of the neural network, compressed kernel data is streamed from an onboard storage to the decompression unit. The decompression unit includes multiple decompression cores. The decompression unit selectively configures the decompression cores to utilize a plurality of decompression algorithms and switches between the multiple decompression algorithms on-the-fly to properly decompress the compressed kernel data in a lossless manner.

Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and iteration control circuitry. The convolutional accelerator, in operation, convolves a kernel with a streaming feature data tensor. The convolving includes decomposing the kernel into a plurality of sub-kernels and iteratively convolving the sub-kernels with respective sub-tensors of the streamed feature data tensor. The iteration control circuitry, in operation, defines respective windows of the streamed feature data tensors, the windows corresponding to the sub-tensors.

Abstract: A device includes a plurality of hardware accelerator islands. The accelerator islands have a plurality of processing elements, a plurality of streaming engines, and a stream switch coupled to the plurality of processing elements and to the plurality of streaming engines. The stream switch streams data between the plurality of processing elements of the accelerator island, and between the plurality of streaming engines of the accelerator island and the plurality of processing elements of the accelerator island. Unidirectional stream switch connections (SSCONNs) are coupled between pairs of stream switches of the plurality of accelerator islands. The stream switches of the plurality of hardware accelerator islands and the SSCONNs form a run-time reconfigurable interconnection mesh between the plurality of processing elements of the plurality of hardware accelerator islands.

Abstract: An input filtering stage for a processing unit in a hardware accelerator is disclosed. A hardware accelerator includes one or more processing units. Each of the one or more processing units includes a buffer and an input filtering stage. The input filtering stage is configured to receive an input data stream that includes a plurality of input channels. Data selection criteria that indicate one or more input channels of the plurality of input channels are obtained. The one or more input channels from the plurality of input channels are selected based on the data selection criteria and provided to the buffer.

Abstract: A neural network is able to reconfigure hardware accelerators on-the-fly without stopping downstream hardware accelerators. The neural network inserts a reconfiguration tag into the stream of feature data. If the reconfiguration tag matches an identification of a hardware accelerator, a reconfiguration process is initiated. Upstream hardware accelerators are paused while downstream hardware accelerators continue to operate. An epoch controller reconfigures the hardware accelerator via a bus. Normal operation of the neural network then resumes.

Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

Abstract: A device includes a plurality of hardware accelerator islands. The accelerator islands have a plurality of processing elements, a plurality of streaming engines, and a stream switch coupled to the plurality of processing elements and to the plurality of streaming engines. The stream switch streams data between the plurality of processing elements of the accelerator island, and between the plurality of streaming engines of the accelerator island and the plurality of processing elements of the accelerator island. Unidirectional stream switch connections (SSCONNs) are coupled between pairs of stream switches of the plurality of accelerator islands. The stream switches of the plurality of hardware accelerator islands and the SSCONNs form a run-time reconfigurable interconnection mesh between the plurality of processing elements of the plurality of hardware accelerator islands.

Abstract: A stream switch includes a data router, configuration registers, and arbitration logic. The data router has a plurality of input ports, each having a plurality of associated virtual input channels, and a plurality of output ports, each having a plurality of associated virtual output channels. The data router transmits data streams from input ports to one or more output ports of the plurality of output ports. The configuration registers store configuration data associated with the virtual output channels of the respective output ports of the plurality of output ports. The stored configuration data identifies a source input port and virtual input channel ID associated with the virtual output channel of the output port. The arbitration logic allocates bandwidth of the data router based on request signals associated with virtual input channels of the input ports and the configuration data associated with the virtual output channels.

Abstract: A hardware accelerator includes a plurality of functional circuits, a stream switch, one or more data reshape units coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and one or more In-Memory Computing (IMC) clusters coupled to the stream switch. In operation, inactive IMC devices of at least a subset of the one or more IMC clusters are accessible to at least a subset of the one or more data reshape units, via memory interface independent from the stream switch, to serve as at least part of Tightly-Coupled Memory (TCM) dedicated to at least one of the one or more data reshape units.

Abstract: A hardware accelerator includes a plurality of functional circuits, a stream switch, a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors a set of data signals to and from the stream switch via wired probes and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.

Abstract: A hardware accelerator includes a plurality of functional circuits, a stream switch, and a plurality of neural network processing cores coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, wherein the neural network processing cores include at least one sender core having a buffer whose buffer content is sharable with at least one receiver core of the neural network processing cores via at least one of a dedicated output stream link or dedicated virtual channel on a pre-existing output stream link, and wherein the at least one of the dedicated output stream link or dedicated virtual channel is dedicated to sharing the buffer content via the stream switch.

Abstract: A convolutional neural network includes convolution circuitry. The convolution circuitry performs convolution operations on input tensor values. The convolutional neural network includes requantization circuitry that requantizes convolution values output from the convolution circuitry.

Abstract: A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task.

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

Abstract: A convolutional neural network includes convolution circuitry. The convolution circuitry performs convolution operations on input tensor values. The convolutional neural network includes requantization circuitry that requantizes convolution values output from the convolution circuitry.

Abstract: A device includes a plurality of hardware accelerator islands. The accelerator islands have a plurality of processing elements, a plurality of streaming engines, and a stream switch coupled to the plurality of processing elements and to the plurality of streaming engines. The stream switch streams data between the plurality of processing elements of the accelerator island, and between the plurality of streaming engines of the accelerator island and the plurality of processing elements of the accelerator island. Unidirectional stream switch connections (SSCONNs) are coupled between pairs of stream switches of the plurality of accelerator islands. The stream switches of the plurality of hardware accelerator islands and the SSCONNs form a run-time reconfigurable interconnection mesh between the plurality of processing elements of the plurality of hardware accelerator islands.

Abstract: A hardware accelerator includes a plurality of functional circuits, a stream switch, a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors a set of data signals to and from the stream switch via wired probes and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.